📄 ifx_swdrv.h
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/******************************************************************************
Copyright (c) 2004, Infineon Technologies. All rights reserved.
No Warranty
Because the program is licensed free of charge, there is no warranty for
the program, to the extent permitted by applicable law. Except when
otherwise stated in writing the copyright holders and/or other parties
provide the program "as is" without warranty of any kind, either
expressed or implied, including, but not limited to, the implied
warranties of merchantability and fitness for a particular purpose. The
entire risk as to the quality and performance of the program is with
you. should the program prove defective, you assume the cost of all
necessary servicing, repair or correction.
In no event unless required by applicable law or agreed to in writing
will any copyright holder, or any other party who may modify and/or
redistribute the program as permitted above, be liable to you for
damages, including any general, special, incidental or consequential
damages arising out of the use or inability to use the program
(including but not limited to loss of data or data being rendered
inaccurate or losses sustained by you or third parties or a failure of
the program to operate with any other programs), even if such holder or
other party has been advised of the possibility of such damages.
******************************************************************************
Module : ifx_swdrv.h
Date : 2004-09-01
Description :
Remarks:
*****************************************************************************/
#ifndef _IFX_SWDRV_H_
#define _IFX_SWDRV_H_
#define ifx_printf(x) printk x
/* command codes */
#define ADM_SW_SMI_READ 0x02
#define ADM_SW_SMI_WRITE 0x01
#define ADM_SW_SMI_START 0x01
#define ADM_SW_EEPROM_READ 0x02 // add - 06/23/05,bolo
#define ADM_SW_EEPROM_WRITE 0x01
#define ADM_SW_EEPROM_WRITE_ENABLE 0x03
#define ADM_SW_EEPROM_WRITE_DISABLE 0x00
#define EEPROM_TYPE 8 // for 93C66
/* bit masks */
#define ADM_SW_BIT_MASK_1 0x00000001
#define ADM_SW_BIT_MASK_2 0x00000002
#define ADM_SW_BIT_MASK_4 0x00000008
#define ADM_SW_BIT_MASK_10 0x00000200
#define ADM_SW_BIT_MASK_16 0x00008000
#define ADM_SW_BIT_MASK_32 0x80000000
/* delay timers */
#define ADM_SW_MDC_DOWN_DELAY 5
#define ADM_SW_MDC_UP_DELAY 5
#define ADM_SW_CS_DELAY 5
/* MDIO modes */
#define ADM_SW_MDIO_OUTPUT 1
#define ADM_SW_MDIO_INPUT 0
#define ADM_SW_MAX_PORT_NUM 5
#define ADM_SW_MAX_VLAN_NUM 15
/* registers */
#define ADM_SW_PORT0_CONF 0x1
#define ADM_SW_PORT1_CONF 0x3
#define ADM_SW_PORT2_CONF 0x5
#define ADM_SW_PORT3_CONF 0x7
#define ADM_SW_PORT4_CONF 0x8
#define ADM_SW_PORT5_CONF 0x9
#define ADM_SW_VLAN_MODE 0x11
#define ADM_SW_MAC_LOCK 0x12
#define ADM_SW_VLAN0_CONF 0x13
#define ADM_SW_PORT0_PVID 0x28
#define ADM_SW_PORT1_PVID 0x29
#define ADM_SW_PORT2_PVID 0x2a
#define ADM_SW_PORT34_PVID 0x2b
#define ADM_SW_PORT5_PVID 0x2c
#define ADM_SW_PHY_RESET 0x2f
#define ADM_SW_MISC_CONF 0x30
#define ADM_SW_BNDWDH_CTL0 0x31
#define ADM_SW_BNDWDH_CTL1 0x32
#define ADM_SW_BNDWDH_CTL_ENA 0x33
/* port modes */
#define ADM_SW_PORT_FLOWCTL 0x1 /* 802.3x flow control */
#define ADM_SW_PORT_AN 0x2 /* auto negotiation */
#define ADM_SW_PORT_100M 0x4 /* 100M */
#define ADM_SW_PORT_FULL 0x8 /* full duplex */
#define ADM_SW_PORT_TAG 0x10 /* output tag on */
#define ADM_SW_PORT_DISABLE 0x20 /* disable port */
#define ADM_SW_PORT_TOS 0x40 /* TOS first */
#define ADM_SW_PORT_PPRI 0x80 /* port based priority first */
#define ADM_SW_PORT_MDIX 0x8000 /* auto MDIX on */
#define ADM_SW_PORT_PVID_SHIFT 10
#define ADM_SW_PORT_PVID_BITS 4
/* VLAN */
#define ADM_SW_VLAN_PORT0 0x1
#define ADM_SW_VLAN_PORT1 0x2
#define ADM_SW_VLAN_PORT2 0x10
#define ADM_SW_VLAN_PORT3 0x40
#define ADM_SW_VLAN_PORT4 0x80
#define ADM_SW_VLAN_PORT5 0x100
unsigned int ifx_sw_conf[ADM_SW_MAX_PORT_NUM+1] = \
{ADM_SW_PORT0_CONF, ADM_SW_PORT1_CONF, ADM_SW_PORT2_CONF, \
ADM_SW_PORT3_CONF, ADM_SW_PORT4_CONF, ADM_SW_PORT5_CONF};
unsigned int ifx_sw_bits[8] = \
{0x1, 0x3, 0x7, 0xf, 0x1f, 0x3f, 0x7f, 0xff};
unsigned int ifx_sw_vlan_port[6] = {0, 2, 4, 6, 7, 8};
/*
mdc pulse
0 -> 1 -> 0
*/
static void ifx_sw_mdc_pulse(void)
{
ifx_mdc_lo();
udelay(ADM_SW_MDC_DOWN_DELAY);
ifx_mdc_hi();
udelay(ADM_SW_MDC_UP_DELAY);
ifx_mdc_lo();
}
/*
mdc toggle
1 -> 0
*/
static void ifx_sw_mdc_toggle(void)
{
ifx_mdc_hi();
udelay(ADM_SW_MDC_UP_DELAY);
ifx_mdc_lo();
udelay(ADM_SW_MDC_DOWN_DELAY);
}
/*
read value from ADM6996I/M internal registers
serial registers start at 0x200 (addr bit 9 = 1b)
EEPROM registers -> 16bits; Serial registers -> 32bits
*/
static int ifx_sw_read(unsigned int addr, unsigned int *dat)
{
unsigned int op;
ifx_gpio_init();
ifx_mdcs_hi();
udelay(ADM_SW_CS_DELAY);
ifx_mdcs_lo();
ifx_mdc_lo();
ifx_mdio_lo();
udelay(ADM_SW_CS_DELAY);
/* preamble, 32 bit 1 */
ifx_mdio_hi();
op = ADM_SW_BIT_MASK_32;
while (op)
{
ifx_sw_mdc_pulse();
op >>= 1;
}
/* command start (01b) */
op = ADM_SW_BIT_MASK_2;
while (op)
{
if (op & ADM_SW_SMI_START)
ifx_mdio_hi();
else
ifx_mdio_lo();
ifx_sw_mdc_pulse();
op >>= 1;
}
/* read command (10b) */
op = ADM_SW_BIT_MASK_2;
while (op)
{
if (op & ADM_SW_SMI_READ)
ifx_mdio_hi();
else
ifx_mdio_lo();
ifx_sw_mdc_pulse();
op >>= 1;
}
/* send address A9 ~ A0 */
op = ADM_SW_BIT_MASK_10;
while (op)
{
if (op & addr)
ifx_mdio_hi();
else
ifx_mdio_lo();
ifx_sw_mdc_pulse();
op >>= 1;
}
/* turnaround bits */
op = ADM_SW_BIT_MASK_2;
ifx_mdio_hi();
while (op)
{
ifx_sw_mdc_pulse();
op >>= 1;
}
udelay(ADM_SW_MDC_DOWN_DELAY);
/* set MDIO pin to input mode */
ifx_mdio_mode(ADM_SW_MDIO_INPUT);
/* start read data */
*dat = 0;
op = ADM_SW_BIT_MASK_16; // Set ADM_SW_BIT_MASK_32 when 32-bit SMI access is configured on the board
while (op)
{
*dat <<= 1;
if (ifx_sw_mdio_readbit()) *dat |= 1;
ifx_sw_mdc_toggle();
op >>= 1;
}
/* set MDIO to output mode */
ifx_mdio_mode(ADM_SW_MDIO_OUTPUT);
/* dummy clock */
op = ADM_SW_BIT_MASK_4;
ifx_mdio_lo();
while(op)
{
ifx_sw_mdc_pulse();
op >>= 1;
}
ifx_mdc_lo();
ifx_mdio_lo();
ifx_mdcs_hi();
/* EEPROM registers */
/* mark - 06/23/05,bolo; unmark when ADM_SW_BIT_MASK_32 is set
if (!(addr & 0x200))
{
if (addr % 2)
*dat >>= 16;
else
*dat &= 0xffff;
}
*/
return 0;
}
/*
Write value to ADM6996I/M internal registers
*/
static int ifx_sw_write(unsigned int addr, unsigned int dat)
{
unsigned int op;
ifx_gpio_init();
ifx_mdcs_hi();
udelay(ADM_SW_CS_DELAY);
ifx_mdcs_lo();
ifx_mdc_lo();
ifx_mdio_lo();
udelay(ADM_SW_CS_DELAY);
/* preamble, 32 bit 1 */
ifx_mdio_hi();
op = ADM_SW_BIT_MASK_32;
while (op)
{
ifx_sw_mdc_pulse();
op >>= 1;
}
/* command start (01b) */
op = ADM_SW_BIT_MASK_2;
while (op)
{
if (op & ADM_SW_SMI_START)
ifx_mdio_hi();
else
ifx_mdio_lo();
ifx_sw_mdc_pulse();
op >>= 1;
}
/* write command (01b) */
op = ADM_SW_BIT_MASK_2;
while (op)
{
if (op & ADM_SW_SMI_WRITE)
ifx_mdio_hi();
else
ifx_mdio_lo();
ifx_sw_mdc_pulse();
op >>= 1;
}
/* send address A9 ~ A0 */
op = ADM_SW_BIT_MASK_10;
while (op)
{
if (op & addr)
ifx_mdio_hi();
else
ifx_mdio_lo();
ifx_sw_mdc_pulse();
op >>= 1;
}
/* turnaround bits */
op = ADM_SW_BIT_MASK_2;
ifx_mdio_hi();
while (op)
{
ifx_sw_mdc_pulse();
op >>= 1;
}
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