📄 uart-16sm.lst
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__text_start:
__start:
74 EFCF LDI R28,0xFF
75 E2D1 LDI R29,0x21
76 BFCD OUT 0x3D,R28
77 BFDE OUT 0x3E,R29
78 51CE SUBI R28,0x1E
79 40D0 SBCI R29,0
7A EA0A LDI R16,0xAA
7B 8308 STD Y+0,R16
7C 2400 CLR R0
7D E0E4 LDI R30,4
7E E0F2 LDI R31,2
7F E012 LDI R17,2
80 32EE CPI R30,0x2E
81 07F1 CPC R31,R17
82 F011 BEQ 0x0085
83 9201 ST R0,Z+
84 CFFB RJMP 0x0080
85 8300 STD Z+0,R16
86 EEE4 LDI R30,0xE4
87 E0F0 LDI R31,0
88 E0A0 LDI R26,0
89 E0B2 LDI R27,2
8A E010 LDI R17,0
8B E000 LDI R16,0
8C BF0B OUT 0x3B,R16
8D 3EE8 CPI R30,0xE8
8E 07F1 CPC R31,R17
8F F021 BEQ 0x0094
90 95C8 LPM
91 9631 ADIW R30,1
92 920D ST R0,X+
93 CFF9 RJMP 0x008D
94 940E 0109 CALL _main
_exit:
96 CFFF RJMP _exit
_uart_rx_isr:
97 922A ST R2,-Y
98 923A ST R3,-Y
99 938A ST R24,-Y
9A 939A ST R25,-Y
9B 93EA ST R30,-Y
9C 93FA ST R31,-Y
9D B62F IN R2,0x3F
9E 922A ST R2,-Y
FILE: C:\+samples-16small\UART-16sm\uart-16sm.c
(0001) // Title: UART-16sm.c
(0002) // Operation:
(0003) // This program make echo to PC sending in Baudrate 38400
(0004) // it receives sending from PC and sends the received one back to PC
(0005) // The LED group1 (the left one) makes counting on received data
(0006) // The LED group2 display the received data in binary
(0007) // Attention: A terminal program "Tera Term Pro" is contained in CD
(0008) // for PC to communicate with the AVR Study Board
(0009)
(0010) /* UCSRA: Control & Status Register A
(0011) b7-RXC: USART receive complete
(0012) b6-TXC: USART transmit complete
(0013) b5-UDRE: USART Data register empty
(0014) b4-FE: Frame Error
(0015) b3-DOR: Data overtun
(0016) b2-PE: Parity error
(0017) b1-U2X: double the USART transmission speed
(0018) b0-MPCM: multi-processor communication mode
(0019)
(0020) USARB
(0021) * b7-RXCIE: RX complete interrupt enable
(0022) b6-TXCIE: TX complete interrupt enable
(0023) b5-UDRIE: USART data register empty interrupt enable
(0024) * b4-RXEN: Receiver enable
(0025) * b3-TXEN: Transmitter enable
(0026) b2-UCSZ2: chracter size ------->0
(0027) b1-RXB8 receive data bit 8
(0028) b0-TXB8: Transmit data 8
(0029)
(0030) UCSRC
(0031) * b7-URSEL: register select 0/UBRRH, 1/UCSRC
(0032) b6-UMSEL: USART mode select 0/Asyn 1/Synchronous
(0033) b5-UPM1: -------- Parity mode 00/disable, 01 reserved
(0034) b4-UPM0: -------- 10 even, 11 odd
(0035) b3-USBS: stop bit selection 0/1-bit, 1/2-bit
(0036) * b2-UCSZ1 --------> 1
(0037) * b1-UCSZ0 --------> 1
(0038) b0-UCPOL: clock polarity 0 rising XCK edge, 1 falling XCK edge
(0039) */
(0040)
(0041)
(0042) #include <iom16v.h>
(0043) #include <macros.h>
(0044)
(0045) #pragma interrupt_handler uart_rx_isr: 12
(0046)
(0047) unsigned char RecBuf[40];
(0048) int rec_head=0, rec_tail=0;
(0049) unsigned rec_data;
(0050)
(0051) void uart_rx_isr(void)
(0052) {
(0053) RecBuf[rec_head]=UDR;
9F E086 LDI R24,6
A0 E092 LDI R25,2
A1 91E0 0200 LDS R30,rec_head
A3 91F0 0201 LDS R31,rec_head+1
A5 0FE8 ADD R30,R24
A6 1FF9 ADC R31,R25
A7 B02C IN R2,0x0C
A8 8220 STD Z+0,R2
(0054) rec_head++;
A9 9180 0200 LDS R24,rec_head
AB 9190 0201 LDS R25,rec_head+1
AD 9601 ADIW R24,1
AE 9390 0201 STS rec_head+1,R25
B0 9380 0200 STS rec_head,R24
(0055) if(rec_head>=40)
B2 3288 CPI R24,0x28
B3 E0E0 LDI R30,0
B4 079E CPC R25,R30
B5 F034 BLT 0x00BC
(0056) rec_head=0;
B6 2422 CLR R2
B7 2433 CLR R3
B8 9230 0201 STS rec_head+1,R3
BA 9220 0200 STS rec_head,R2
BC 9029 LD R2,Y+
BD BE2F OUT 0x3F,R2
BE 91F9 LD R31,Y+
BF 91E9 LD R30,Y+
C0 9199 LD R25,Y+
C1 9189 LD R24,Y+
C2 9039 LD R3,Y+
C3 9029 LD R2,Y+
C4 9518 RETI
(0057) }
(0058)
(0059) void port_init(void)
(0060) {
(0061) DDRA = 0xFF; //set PortA output
_port_init:
C5 EF8F LDI R24,0xFF
C6 BB8A OUT 0x1A,R24
(0062) DDRB = 0xff; //set PORTB output
C7 BB87 OUT 0x17,R24
(0063) DDRC = 0x00; //set PORTC output
C8 2422 CLR R2
C9 BA24 OUT 0x14,R2
(0064) PORTC = 0xff;
CA BB85 OUT 0x15,R24
(0065) DDRD = 0x7f; //set PD.7 input for RX
CB E78F LDI R24,0x7F
CC BB81 OUT 0x11,R24
CD 9508 RET
_USART_init:
CE 9722 SBIW R28,2
(0066) }
(0067)
(0068) void USART_init(void)
(0069) {
(0070) UCSRB=0x00;
CF 2422 CLR R2
D0 B82A OUT 0x0A,R2
(0071) UCSRA=0x00;
D1 B82B OUT 0x0B,R2
(0072) UCSRB=0b10011000; //b7: RXCIE enabeled, b4: RXEN enabled, B3: TXEN enabled
D2 E988 LDI R24,0x98
D3 B98A OUT 0x0A,R24
(0073) UBRRH=0x00; //
D4 BC20 OUT 0x20,R2
(0074) //Crystal=16MHx
(0075) //UBRRL=103; //Bausdrate=9600 tested work fine
(0076) //UBRRL=51; //Baudrate=19200 tested work fine
(0077) UBRRL=25; //Baudrate=38400 tested work fine
D5 E189 LDI R24,0x19
D6 B989 OUT 0x09,R24
(0078) //UBRRL=8; //Baurate=115200 tested work fine
(0079) UCSRC=0b10000110; //Asyn, No parity, 1-stop, 8-bit, rising edge
D7 E886 LDI R24,0x86
D8 BD80 OUT 0x20,R24
(0080) memset(RecBuf, 0, sizeof(RecBuf));
D9 E288 LDI R24,0x28
DA E090 LDI R25,0
DB 8399 STD Y+1,R25
DC 8388 STD Y+0,R24
DD 2722 CLR R18
DE 2733 CLR R19
DF E006 LDI R16,6
E0 E012 LDI R17,2
E1 940E 0154 CALL _memset
(0081) rec_head=0;
E3 2422 CLR R2
E4 2433 CLR R3
E5 9230 0201 STS rec_head+1,R3
E7 9220 0200 STS rec_head,R2
(0082) rec_tail=0;
E9 9230 0203 STS rec_tail+1,R3
EB 9220 0202 STS rec_tail,R2
ED 9622 ADIW R28,2
EE 9508 RET
_delay:
i --> R20
j --> R22
count --> R16
EF 940E 015F CALL push_xgsetF000
(0083) }
(0084)
(0085) void delay(int count)
(0086) {
(0087) int i, j;
(0088) for(i=count; i>0; i--)
F1 01A8 MOVW R20,R16
F2 C00B RJMP 0x00FE
(0089) for(j=10; j>0; j--)
F3 E06A LDI R22,0xA
F4 E070 LDI R23,0
F5 5061 SUBI R22,1
F6 4070 SBCI R23,0
F7 2422 CLR R2
F8 2433 CLR R3
F9 1626 CP R2,R22
FA 0637 CPC R3,R23
FB F3CC BLT 0x00F5
FC 5041 SUBI R20,1
FD 4050 SBCI R21,0
FE 2422 CLR R2
FF 2433 CLR R3
100 1624 CP R2,R20
101 0635 CPC R3,R21
102 F384 BLT 0x00F3
103 940C 0164 JMP pop_xgsetF000
(0090) ;
(0091) }
(0092)
(0093) void transmit(unsigned char abyte)
(0094) {
(0095) UDR=abyte;
_transmit:
abyte --> R16
105 B90C OUT 0x0C,R16
(0096) while(!(UCSRA&0b01000000)) //b6=1 TXE
106 9B5E SBIS 0x0B,6
107 CFFE RJMP 0x0106
108 9508 RET
(0097) ;
(0098) }
(0099) //*****************************************************************
(0100) void main(void)
(0101) {
(0102) unsigned char outa=0b01010101, outb=0b10101010, outc=0x00, outd=0x00;
_main:
outd --> R10
outc --> R10
outb --> R20
outa --> R20
dswin --> R10
109 EA4A LDI R20,0xAA
10A 24AA CLR R10
(0103) int dswin;
(0104) port_init();
10B DFB9 RCALL _port_init
(0105) USART_init();
10C DFC1 RCALL _USART_init
(0106) SEI();
10D 9478 BSET 7
10E C043 RJMP 0x0152
(0107) while(1)
(0108) {
(0109) WDR(); //Watchdog reset
10F 95A8 WDR
(0110) if(rec_head!=rec_tail)
110 9020 0202 LDS R2,rec_tail
112 9030 0203 LDS R3,rec_tail+1
114 9040 0200 LDS R4,rec_head
116 9050 0201 LDS R5,rec_head+1
118 1442 CP R4,R2
119 0453 CPC R5,R3
11A F1B9 BEQ 0x0152
(0111) {
(0112) rec_data=RecBuf[rec_tail];
11B E086 LDI R24,6
11C E092 LDI R25,2
11D 01F1 MOVW R30,R2
11E 0FE8 ADD R30,R24
11F 1FF9 ADC R31,R25
120 8020 LDD R2,Z+0
121 2433 CLR R3
122 9230 0205 STS rec_data+1,R3
124 9220 0204 STS rec_data,R2
(0113) rec_tail++;
126 9180 0202 LDS R24,rec_tail
128 9190 0203 LDS R25,rec_tail+1
12A 9601 ADIW R24,1
12B 9390 0203 STS rec_tail+1,R25
12D 9380 0202 STS rec_tail,R24
(0114) if(rec_tail>=40)
12F 3288 CPI R24,0x28
130 E0E0 LDI R30,0
131 079E CPC R25,R30
132 F02C BLT 0x0138
(0115) rec_tail=0;
133 2422 CLR R2
134 9230 0203 STS rec_tail+1,R3
136 9220 0202 STS rec_tail,R2
(0116)
(0117) dswin=rec_head<<2;
138 90A0 0200 LDS R10,rec_head
13A 90B0 0201 LDS R11,rec_head+1
13C 0CAA LSL R10
13D 1CBB ROL R11
13E 0CAA LSL R10
13F 1CBB ROL R11
(0118) PORTD=dswin;
140 BAA2 OUT 0x12,R10
(0119) PORTA=rec_data;
141 9020 0204 LDS R2,rec_data
143 9030 0205 LDS R3,rec_data+1
145 BA2B OUT 0x1B,R2
(0120) transmit(rec_data);
146 2D02 MOV R16,R2
147 DFBD RCALL _transmit
(0121) if(rec_data==13)
148 9180 0204 LDS R24,rec_data
14A 9190 0205 LDS R25,rec_data+1
14C 308D CPI R24,0xD
14D E0E0 LDI R30,0
14E 079E CPC R25,R30
14F F411 BNE 0x0152
(0122) transmit(10);
FILE: <library>
150 E00A LDI R16,0xA
151 DFB3 RCALL _transmit
152 CFBC RJMP 0x010F
153 9508 RET
_memset:
154 8188 LDD R24,Y+0
155 8199 LDD R25,Y+1
156 3080 CPI R24,0
157 0789 CPC R24,R25
158 F029 BEQ 0x015E
159 2FE0 MOV R30,R16
15A 2FF1 MOV R31,R17
15B 9321 ST R18,Z+
15C 9701 SBIW R24,1
15D F7E9 BNE 0x015B
15E 9508 RET
push_xgsetF000:
15F 937A ST R23,-Y
160 936A ST R22,-Y
161 935A ST R21,-Y
162 934A ST R20,-Y
163 9508 RET
pop_xgsetF000:
164 9149 LD R20,Y+
165 9159 LD R21,Y+
166 9169 LD R22,Y+
167 9179 LD R23,Y+
168 9508 RET
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