📄 uart-16sm.s
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.module uart-16sm.c
.area text(rom, con, rel)
.dbfile C:\+samples-16small\UART-16sm\uart-16sm.c
.area vector(rom, abs)
.org 44
jmp _uart_rx_isr
.area text(rom, con, rel)
.dbfile C:\+samples-16small\UART-16sm\uart-16sm.c
.area data(ram, con, rel)
.dbfile C:\+samples-16small\UART-16sm\uart-16sm.c
_rec_head::
.blkb 2
.area idata
.word 0
.area data(ram, con, rel)
.dbfile C:\+samples-16small\UART-16sm\uart-16sm.c
.dbsym e rec_head _rec_head I
_rec_tail::
.blkb 2
.area idata
.word 0
.area data(ram, con, rel)
.dbfile C:\+samples-16small\UART-16sm\uart-16sm.c
.dbsym e rec_tail _rec_tail I
.area text(rom, con, rel)
.dbfile C:\+samples-16small\UART-16sm\uart-16sm.c
.dbfunc e uart_rx_isr _uart_rx_isr fV
.even
_uart_rx_isr::
st -y,R2
st -y,R3
st -y,R24
st -y,R25
st -y,R30
st -y,R31
in R2,0x3f
st -y,R2
.dbline -1
.dbline 52
; // Title: UART-16sm.c
; // Operation:
; // This program make echo to PC sending in Baudrate 38400
; // it receives sending from PC and sends the received one back to PC
; // The LED group1 (the left one) makes counting on received data
; // The LED group2 display the received data in binary
; // Attention: A terminal program "Tera Term Pro" is contained in CD
; // for PC to communicate with the AVR Study Board
;
; /* UCSRA: Control & Status Register A
; b7-RXC: USART receive complete
; b6-TXC: USART transmit complete
; b5-UDRE: USART Data register empty
; b4-FE: Frame Error
; b3-DOR: Data overtun
; b2-PE: Parity error
; b1-U2X: double the USART transmission speed
; b0-MPCM: multi-processor communication mode
;
; USARB
; * b7-RXCIE: RX complete interrupt enable
; b6-TXCIE: TX complete interrupt enable
; b5-UDRIE: USART data register empty interrupt enable
; * b4-RXEN: Receiver enable
; * b3-TXEN: Transmitter enable
; b2-UCSZ2: chracter size ------->0
; b1-RXB8 receive data bit 8
; b0-TXB8: Transmit data 8
;
; UCSRC
; * b7-URSEL: register select 0/UBRRH, 1/UCSRC
; b6-UMSEL: USART mode select 0/Asyn 1/Synchronous
; b5-UPM1: -------- Parity mode 00/disable, 01 reserved
; b4-UPM0: -------- 10 even, 11 odd
; b3-USBS: stop bit selection 0/1-bit, 1/2-bit
; * b2-UCSZ1 --------> 1
; * b1-UCSZ0 --------> 1
; b0-UCPOL: clock polarity 0 rising XCK edge, 1 falling XCK edge
; */
;
;
; #include <iom16v.h>
; #include <macros.h>
;
; #pragma interrupt_handler uart_rx_isr: 12
;
; unsigned char RecBuf[40];
; int rec_head=0, rec_tail=0;
; unsigned rec_data;
;
; void uart_rx_isr(void)
; {
.dbline 53
; RecBuf[rec_head]=UDR;
ldi R24,<_RecBuf
ldi R25,>_RecBuf
lds R30,_rec_head
lds R31,_rec_head+1
add R30,R24
adc R31,R25
in R2,0xc
std z+0,R2
.dbline 54
; rec_head++;
lds R24,_rec_head
lds R25,_rec_head+1
adiw R24,1
sts _rec_head+1,R25
sts _rec_head,R24
.dbline 55
; if(rec_head>=40)
cpi R24,40
ldi R30,0
cpc R25,R30
brlt L2
X0:
.dbline 56
; rec_head=0;
clr R2
clr R3
sts _rec_head+1,R3
sts _rec_head,R2
L2:
.dbline -2
L1:
.dbline 0 ; func end
ld R2,y+
out 0x3f,R2
ld R31,y+
ld R30,y+
ld R25,y+
ld R24,y+
ld R3,y+
ld R2,y+
reti
.dbend
.dbfunc e port_init _port_init fV
.even
_port_init::
.dbline -1
.dbline 60
; }
;
; void port_init(void)
; {
.dbline 61
; DDRA = 0xFF; //set PortA output
ldi R24,255
out 0x1a,R24
.dbline 62
; DDRB = 0xff; //set PORTB output
out 0x17,R24
.dbline 63
; DDRC = 0x00; //set PORTC output
clr R2
out 0x14,R2
.dbline 64
; PORTC = 0xff;
out 0x15,R24
.dbline 65
; DDRD = 0x7f; //set PD.7 input for RX
ldi R24,127
out 0x11,R24
.dbline -2
L4:
.dbline 0 ; func end
ret
.dbend
.dbfunc e USART_init _USART_init fV
.even
_USART_init::
sbiw R28,2
.dbline -1
.dbline 69
; }
;
; void USART_init(void)
; {
.dbline 70
; UCSRB=0x00;
clr R2
out 0xa,R2
.dbline 71
; UCSRA=0x00;
out 0xb,R2
.dbline 72
; UCSRB=0b10011000; //b7: RXCIE enabeled, b4: RXEN enabled, B3: TXEN enabled
ldi R24,152
out 0xa,R24
.dbline 73
; UBRRH=0x00; //
out 0x20,R2
.dbline 77
; //Crystal=16MHx
; //UBRRL=103; //Bausdrate=9600 tested work fine
; //UBRRL=51; //Baudrate=19200 tested work fine
; UBRRL=25; //Baudrate=38400 tested work fine
ldi R24,25
out 0x9,R24
.dbline 79
; //UBRRL=8; //Baurate=115200 tested work fine
; UCSRC=0b10000110; //Asyn, No parity, 1-stop, 8-bit, rising edge
ldi R24,134
out 0x20,R24
.dbline 80
; memset(RecBuf, 0, sizeof(RecBuf));
ldi R24,40
ldi R25,0
std y+1,R25
std y+0,R24
clr R18
clr R19
ldi R16,<_RecBuf
ldi R17,>_RecBuf
xcall _memset
.dbline 81
; rec_head=0;
clr R2
clr R3
sts _rec_head+1,R3
sts _rec_head,R2
.dbline 82
; rec_tail=0;
sts _rec_tail+1,R3
sts _rec_tail,R2
.dbline -2
L5:
.dbline 0 ; func end
adiw R28,2
ret
.dbend
.dbfunc e delay _delay fV
; i -> R20,R21
; j -> R22,R23
; count -> R16,R17
.even
_delay::
xcall push_xgsetF000
.dbline -1
.dbline 86
; }
;
; void delay(int count)
; {
.dbline 88
; int i, j;
; for(i=count; i>0; i--)
movw R20,R16
xjmp L10
L7:
.dbline 89
; for(j=10; j>0; j--)
ldi R22,10
ldi R23,0
L11:
.dbline 90
; ;
L12:
.dbline 89
subi R22,1
sbci R23,0
.dbline 89
clr R2
clr R3
cp R2,R22
cpc R3,R23
brlt L11
X1:
L8:
.dbline 88
subi R20,1
sbci R21,0
L10:
.dbline 88
clr R2
clr R3
cp R2,R20
cpc R3,R21
brlt L7
X2:
.dbline -2
L6:
.dbline 0 ; func end
xjmp pop_xgsetF000
.dbsym r i 20 I
.dbsym r j 22 I
.dbsym r count 16 I
.dbend
.dbfunc e transmit _transmit fV
; abyte -> R16
.even
_transmit::
.dbline -1
.dbline 94
; }
;
; void transmit(unsigned char abyte)
; {
.dbline 95
; UDR=abyte;
out 0xc,R16
L16:
.dbline 97
; while(!(UCSRA&0b01000000)) //b6=1 TXE
; ;
L17:
.dbline 96
sbis 0xb,6
rjmp L16
X3:
.dbline -2
L15:
.dbline 0 ; func end
ret
.dbsym r abyte 16 c
.dbend
.dbfunc e main _main fV
; outd -> R10
; outc -> R10
; outb -> R20
; outa -> R20
; dswin -> R10,R11
.even
_main::
.dbline -1
.dbline 101
; }
; //*****************************************************************
; void main(void)
; {
.dbline 102
; unsigned char outa=0b01010101, outb=0b10101010, outc=0x00, outd=0x00;
.dbline 102
ldi R20,170
.dbline 102
clr R10
.dbline 102
.dbline 104
; int dswin;
; port_init();
xcall _port_init
.dbline 105
; USART_init();
xcall _USART_init
.dbline 106
; SEI();
sei
xjmp L21
L20:
.dbline 108
; while(1)
; {
.dbline 109
; WDR(); //Watchdog reset
wdr
.dbline 110
; if(rec_head!=rec_tail)
lds R2,_rec_tail
lds R3,_rec_tail+1
lds R4,_rec_head
lds R5,_rec_head+1
cp R4,R2
cpc R5,R3
breq L23
X4:
.dbline 111
; {
.dbline 112
; rec_data=RecBuf[rec_tail];
ldi R24,<_RecBuf
ldi R25,>_RecBuf
movw R30,R2
add R30,R24
adc R31,R25
ldd R2,z+0
clr R3
sts _rec_data+1,R3
sts _rec_data,R2
.dbline 113
; rec_tail++;
lds R24,_rec_tail
lds R25,_rec_tail+1
adiw R24,1
sts _rec_tail+1,R25
sts _rec_tail,R24
.dbline 114
; if(rec_tail>=40)
cpi R24,40
ldi R30,0
cpc R25,R30
brlt L25
X5:
.dbline 115
; rec_tail=0;
clr R2
sts _rec_tail+1,R3
sts _rec_tail,R2
L25:
.dbline 117
;
; dswin=rec_head<<2;
lds R10,_rec_head
lds R11,_rec_head+1
lsl R10
rol R11
lsl R10
rol R11
.dbline 118
; PORTD=dswin;
out 0x12,R10
.dbline 119
; PORTA=rec_data;
lds R2,_rec_data
lds R3,_rec_data+1
out 0x1b,R2
.dbline 120
; transmit(rec_data);
mov R16,R2
xcall _transmit
.dbline 121
; if(rec_data==13)
lds R24,_rec_data
lds R25,_rec_data+1
cpi R24,13
ldi R30,0
cpc R25,R30
brne L27
X6:
.dbline 122
; transmit(10);
ldi R16,10
xcall _transmit
L27:
.dbline 124
;
; }
L23:
.dbline 125
; }
L21:
.dbline 107
xjmp L20
X7:
.dbline -2
L19:
.dbline 0 ; func end
ret
.dbsym r outd 10 c
.dbsym r outc 10 c
.dbsym r outb 20 c
.dbsym r outa 20 c
.dbsym r dswin 10 I
.dbend
.area bss(ram, con, rel)
.dbfile C:\+samples-16small\UART-16sm\uart-16sm.c
_rec_data::
.blkb 2
.dbsym e rec_data _rec_data i
_RecBuf::
.blkb 40
.dbsym e RecBuf _RecBuf A[40:40]c
; }
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