a8237.csf.rpt

8237 VHDL代码

a8237 - Quartus II Compilation Report File
-------------------------------------------------------------------------------

+----------------------------------------------------------------------+
|Report Information                                                    |
+------------------+---------------------------------------------------+
|Project           |d:\figureitout\random\test_8237\db\a8237.quartus_db|
|Compiler Settings |a8237                                              |
|Quartus II Version|2.1 Build 166 07/08/2002 SJ Full Version           |
+------------------+---------------------------------------------------+

Table of Contents
    Compilation Report
        Legal Notice
        Project Settings
            General Settings
        Results for "a8237" Compiler Settings
            Summary
            Compiler Settings
            Messages
            Processing Time

+-----------------------------------------------------------------------------+
|Legal Notice                                                                 |
+-----------------------------------------------------------------------------+
Copyright (C) 1991-2002 Altera Corporation
Any  megafunction  design,  and related netlist (encrypted  or  decrypted),
support information,  device programming or simulation file,  and any other
associated  documentation or information  provided by  Altera  or a partner
under  Altera's   Megafunction   Partnership   Program  may  be  used  only
to program  PLD  devices (but not masked  PLD  devices) from  Altera.   Any
other  use  of such  megafunction  design,  netlist,  support  information,
device programming or simulation file,  or any other  related documentation
or information  is prohibited  for  any  other purpose,  including, but not
limited to  modification,  reverse engineering,  de-compiling, or use  with
any other  silicon devices,  unless such use is  explicitly  licensed under
a separate agreement with  Altera  or a megafunction partner.  Title to the
intellectual property,  including patents,  copyrights,  trademarks,  trade
secrets,  or maskworks,  embodied in any such megafunction design, netlist,
support  information,  device programming or simulation file,  or any other
related documentation or information provided by  Altera  or a megafunction
partner, remains with Altera, the megafunction partner, or their respective
licensors. No other licenses, including any licenses needed under any third
party's intellectual property, are provided herein.


+-----------------------------------------------------------------------------+
|General Settings                                                             |
+-----------------------------------------------------------------------------+
+-----------------+-------------------+
|Option           |Setting            |
+-----------------+-------------------+
|Start date & time|08/27/2002 15:40:22|
|Main task        |Compilation        |
|Settings name    |a8237              |
+-----------------+-------------------+

+-----------------------------------------------------------------------------+
|Summary                                                                      |
+-----------------------------------------------------------------------------+
+-----------------------------------+-------------------+
|Processing status                  |Design not fitted  |
|Timing requirements/analysis status|Timing not analyzed|
|Chip name                          |a8237              |
|Device for compilation             |EP1S25F780C6       |
|Total logic elements               |Not available yet  |
|Total pins                         |Not available yet  |
+-----------------------------------+-------------------+

+-----------------------------------------------------------------------------+
|Compiler Settings                                                            |
+-----------------------------------------------------------------------------+
+------------------------------------------+------------------+
|Option                                    |Setting           |
+------------------------------------------+------------------+
|Chip name                                 |a8237             |
|Family name                               |Stratix           |
|Focus entity name                         ||a8237            |
|Device                                    |EP1S25F780C6      |
|Compilation mode                          |Full              |
|Disk space/compilation speed tradeoff     |Normal            |
|Preserve fewer node names                 |On                |
|Optimize timing                           |Normal Compilation|
|Optimize IOC register placement for timing|On                |
|Generate timing analyses                  |On                |
|Fast Fit compilation                      |Off               |
|SignalProbe compilation                   |Off               |
+------------------------------------------+------------------+

+-----------------------------------------------------------------------------+
|Messages                                                                     |
+-----------------------------------------------------------------------------+
Info: Found 2 design units and 1 entities in source file d:\figureitout\random\test_8237\addr_sync.vhd
  Info: Found design unit 1: addrsync-rtl
  Info: Found entity 1: addrsync
Info: Found 2 design units and 1 entities in source file d:\figureitout\random\test_8237\bar.vhd
  Info: Found design unit 1: bar-rtl
  Info: Found entity 1: bar
Info: Found 2 design units and 1 entities in source file d:\figureitout\random\test_8237\bword.vhd
  Info: Found design unit 1: bword-rtl
  Info: Found entity 1: bword
Info: Found 2 design units and 1 entities in source file d:\figureitout\random\test_8237\car.vhd
  Info: Found design unit 1: car-rtl
  Info: Found entity 1: car
Info: Found 2 design units and 1 entities in source file d:\figureitout\random\test_8237\cmdreg.vhd
  Info: Found design unit 1: cmdreg-rtl
  Info: Found entity 1: cmdreg
Info: Found 2 design units and 1 entities in source file d:\figureitout\random\test_8237\cword.vhd
  Info: Found design unit 1: cword-rtl
  Info: Found entity 1: cword
Info: Found 2 design units and 1 entities in source file d:\figureitout\random\test_8237\data_sync.vhd
  Info: Found design unit 1: datasync-rtl
  Info: Found entity 1: datasync
Info: Found 2 design units and 1 entities in source file d:\figureitout\random\test_8237\dout_mux.vhd
  Info: Found design unit 1: dout_mux-rtl
  Info: Found entity 1: dout_mux
Info: Found 2 design units and 1 entities in source file d:\figureitout\random\test_8237\host_dec.vhd
  Info: Found design unit 1: host_dec-rtl
  Info: Found entity 1: host_dec
Error: VHDL Package Body error at l_conversions_b.vhd(22): package conversions is used but not declared
Error: VHDL error at l_conversions_b.vhd(27): object integer is used but not declared
Error: VHDL error at l_conversions_b.vhd(27): object integer is used but not declared
Error: VHDL error at l_conversions_b.vhd(29): object x is used but not declared
Error: VHDL error at l_conversions_b.vhd(29): object y is used but not declared
Error: VHDL error at l_conversions_b.vhd(29): object x is used but not declared
Error: VHDL error at l_conversions_b.vhd(29): object y is used but not declared
Error: VHDL error at l_conversions_b.vhd(32): object integer is used but not declared
Error: VHDL error at l_conversions_b.vhd(32): object integer is used but not declared
Error: VHDL error at l_conversions_b.vhd(34): object x is used but not declared
Error: VHDL error at l_conversions_b.vhd(34): object y is used but not declared
Error: VHDL error at l_conversions_b.vhd(34): object x is used but not declared
Error: VHDL error at l_conversions_b.vhd(34): object y is used but not declared
Error: VHDL error at l_conversions_b.vhd(47): object positive is used but not declared
Error: VHDL error at l_conversions_b.vhd(48): object positive is used but not declared
Error: VHDL error at l_conversions_b.vhd(48): object positive is used but not declared
Error: VHDL error at l_conversions_b.vhd(51): object size is used but not declared
Error: VHDL error at l_conversions_b.vhd(52): object size is used but not declared
Error: VHDL error at l_conversions_b.vhd(50): object x is used but not declared
Info: Found 0 design units and 0 entities in source file d:\figureitout\random\test_8237\l_conversions_b.vhd
Info: Found 1 design units and 0 entities in source file d:\figureitout\random\test_8237\l_conversions_p.vhd
  Info: Found design unit 1: conversions
Info: Found 7 design units and 3 entities in source file d:\figureitout\random\test_8237\l_synplify.vhd
  Info: Found design unit 1: prim_counter-beh
  Info: Found design unit 2: prim_dff-beh
  Info: Found design unit 3: prim_latch-beh
  Info: Found design unit 4: components
  Info: Found entity 1: prim_counter
  Info: Found entity 2: prim_dff
  Info: Found entity 3: prim_latch
Info: Found 2 design units and 1 entities in source file d:\figureitout\random\test_8237\mask.vhd
  Info: Found design unit 1: mask-rtl
  Info: Found entity 1: mask
Info: Found 2 design units and 1 entities in source file d:\figureitout\random\test_8237\modereg.vhd
  Info: Found design unit 1: modereg-rtl
  Info: Found entity 1: modereg
Info: Found 2 design units and 1 entities in source file d:\figureitout\random\test_8237\rd_sync.vhd
  Info: Found design unit 1: readsync-rtl
  Info: Found entity 1: readsync
Info: Found 2 design units and 1 entities in source file d:\figureitout\random\test_8237\req_enc.vhd
  Info: Found design unit 1: req_enc-rtl
  Info: Found entity 1: req_enc
Info: Found 2 design units and 1 entities in source file d:\figureitout\random\test_8237\request.vhd
  Info: Found design unit 1: request-rtl
  Info: Found entity 1: request
Info: Found 2 design units and 1 entities in source file d:\figureitout\random\test_8237\sequencer.vhd
  Info: Found design unit 1: sequencer-rtl
  Info: Found entity 1: sequencer
Info: Found 2 design units and 1 entities in source file d:\figureitout\random\test_8237\status.vhd
  Info: Found design unit 1: status-rtl
  Info: Found entity 1: status
Info: Found 2 design units and 1 entities in source file d:\figureitout\random\test_8237\tempadd.vhd
  Info: Found design unit 1: tempadd-rtl
  Info: Found entity 1: tempadd
Info: Found 2 design units and 1 entities in source file d:\figureitout\random\test_8237\tempreg.vhd
  Info: Found design unit 1: tempreg-rtl
  Info: Found entity 1: tempreg
Info: Found 2 design units and 1 entities in source file d:\figureitout\random\test_8237\worddec.vhd
  Info: Found design unit 1: worddec-rtl
  Info: Found entity 1: worddec
Info: Found 2 design units and 1 entities in source file d:\figureitout\random\test_8237\wr_sync.vhd
  Info: Found design unit 1: writesync-rtl
  Info: Found entity 1: writesync
Info: Found 2 design units and 1 entities in source file d:\figureitout\random\test_8237\a8237.vhd
  Info: Found design unit 1: a8237-structure
  Info: Found entity 1: a8237
Error: Design a8237: Full compilation was unsuccessful. 19 errors, 0 warnings

+-----------------------------------------------------------------------------+
|Processing Time                                                              |
+-----------------------------------------------------------------------------+
+-----------------+------------+
|Module Name      |Elapsed Time|
+-----------------+------------+
|Database Builder |00:00:03    |
|Logic Synthesizer|00:00:00    |
|Fitter           |00:00:00    |
|Assembler        |00:00:00    |
|Delay Annotator  |00:00:00    |
|Timing Analyzer  |00:00:00    |
|Total            |00:00:03    |
+-----------------+------------+