speaker.vhd

来自「本源码设计了自动电子琴」· VHDL 代码 · 共 37 行

library IEEE; 
use IEEE.STD_LOGIC_1164.ALL; 
use IEEE.STD_LOGIC_ARITH.ALL; 
use IEEE.STD_LOGIC_UNSIGNED.ALL; 
entity speaker is 
Port ( clk1   : in std_logic;                                       
tone1 : in integer range 0 to 16383;             
spks   : out std_logic);                                                 
end speaker; 

architecture Behavioral of speaker is 
signal  fullspks:std_logic;
begin 
genspks:process(clk1,tone1) 
variable count11:integer range 0 to 16383; 
Begin 
     if clk1'event and clk1='1' then 
    if count11=16383 then
        count11:=tone1;
        fullspks<='1';  
      else count11:=count11+1;fullspks<='0'; 
      end if;  
   end if; 
end process; 
delaysps:process(fullspks)    
variable count2 :std_logic:='0'; 
begin 
       if fullspks'event and fullspks='1' then 
            count2:=not count2; 
       if count2='1' then spks<='1'; 
       else spks<='0'; 
       end if; 
    end if; 
end process; 
end Behavioral;