cnt.vhd

来自「本源码设计了自动电子琴」· VHDL 代码 · 共 31 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity cnt is
port(clk,ld:in std_logic;
          d:in std_logic_vector(13 downto 0);
          q:buffer std_logic_vector(13 downto 0);
          z:out std_logic );
end;
architecture one of cnt is
begin
process(clk)
begin
if clk'event and clk='1' then
if ld='1'then
q<=q+1;
else
q<=d;
end if;
end if;
end process;
process(q)
begin
if q="11111111111111"then
z<='1';
else
z<='0';
end if;
end process;
end;