📄 init.lst
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381 00000000 00000100
STrp1 EQU SRASPrechargeTime1:SHL:8
382 00000000 ;
383 00000000 00000000
rSDRAMCON1
EQU 0x00
384 00000000 ;rSDRAMCON1 EQU SCAN1+DRAMEndPtr1+DRAMBasePtr1+STrp1+
STrc1
385 00000000 ;-------------------------------------------------------
------
386 00000000
387 00000000 ;/* -> DRAMCON2 : RAM Bank2 control register */
388 00000000 ;-------------------------------------------------------
------
389 00000000 00000000
EDO_Mode2
EQU 0 ;(EDO)0=Normal, 1=E
DO DRAM
390 00000000 00000000
CasPrechargeTime2
EQU 0 ;(Tcp)0=1cycle,1=2c
ycle
391 00000000 00000001
CasStrobeTime2
EQU 1 ;(Tcs)0=1cycle ~ 3=
4cycle
392 00000000 00000001
DRAMCON2Reserved
EQU 1 ; Must be set to 1
393 00000000 00000000
RAS2CASDelay2
EQU 0 ;(Trc)0=1cycle,1=2c
ycle
ARM Macro Assembler Page 16
394 00000000 00000000
RASPrechargeTime2
EQU 0 ;(Trp)0=1cycle ~ 3=
4clcyle
395 00000000 00060000
DRAMBasePtr2
EQU 0x180:SHL:10 ;=0x14000000
396 00000000 1C000000
DRAMEndPtr2
EQU 0x1C0:SHL:20 ;=0x18000000
397 00000000 00000002
NoColumnAddr2
EQU 2 ;0=8bit,1=9bit,2=10
bit,3=11bits
398 00000000 ;-------------------------------------------------------
------
399 00000000 00000002
Tcs2 EQU CasStrobeTime2:SHL:1
400 00000000 00000000
Tcp2 EQU CasPrechargeTime2:SHL:3
401 00000000 00000010
dumy2 EQU DRAMCON2Reserved:SHL:4
; dummy cycle
402 00000000 00000000
Trc2 EQU RAS2CASDelay2:SHL:7
403 00000000 00000000
Trp2 EQU RASPrechargeTime2:SHL:8
404 00000000 80000000
CAN2 EQU NoColumnAddr2:SHL:30
405 00000000 ;
406 00000000 9C060012
rDRAMCON2
EQU CAN2+DRAMEndPtr2+DRAMBasePtr2+T
rp2+Trc2+Tcp2+Tcs2+dumy2+EDO_Mode2
407 00000000 ;--------------------------
408 00000000 00000001
SRAS2CASDelay2
EQU 1 ;(Trc)0=1cycle,1=2c
ycle
409 00000000 00000001
SRASPrechargeTime2
EQU 1 ;(Trp)0=1cycle ~ 3=
4clcyle
410 00000000 00000000
SNoColumnAddr2
EQU 0 ;0=8bit,1=9bit,2=10
bit,3=11bits
411 00000000 00000000
SCAN2 EQU SNoColumnAddr2:SHL:30
412 00000000 00000080
STrc2 EQU SRAS2CASDelay2:SHL:7
413 00000000 00000100
STrp2 EQU SRASPrechargeTime2:SHL:8
414 00000000 ;
415 00000000 00000000
rSDRAMCON2
EQU 0x00
416 00000000 ;rSDRAMCON2 EQU SCAN2+DRAMEndPtr2+DRAMBasePtr2+STrp2+
STrc2
ARM Macro Assembler Page 17
417 00000000 ;-------------------------------------------------------
------
418 00000000
419 00000000 ;/* -> DRAMCON3 : RAM Bank3 control register */
420 00000000 ;-------------------------------------------------------
------
421 00000000 00000000
EDO_Mode3
EQU 0 ;(EDO)0=Normal, 1=E
DO DRAM
422 00000000 00000000
CasPrechargeTime3
EQU 0 ;(Tcp)0=1cycle,1=2c
ycle
423 00000000 00000001
CasStrobeTime3
EQU 1 ;(Tcs)0=1cycle ~ 3=
4cycle
424 00000000 00000001
DRAMCON3Reserved
EQU 1 ; Must be set to 1
425 00000000 00000000
RAS2CASDelay3
EQU 0 ;(Trc)0=1cycle,1=2c
ycle
426 00000000 00000000
RASPrechargeTime3
EQU 0 ;(Trp)0=1cycle ~ 3=
4clcyle
427 00000000 00070000
DRAMBasePtr3
EQU 0x1C0:SHL:10 ;=0x14000000
428 00000000 20000000
DRAMEndPtr3
EQU 0x200:SHL:20 ;=0x18000000
429 00000000 00000002
NoColumnAddr3
EQU 2 ;0=8bit,1=9bit,2=10
bit,3=11bits
430 00000000 ;-------------------------------------------------------
------
431 00000000 00000002
Tcs3 EQU CasStrobeTime3:SHL:1
432 00000000 00000000
Tcp3 EQU CasPrechargeTime3:SHL:3
433 00000000 00000010
dumy3 EQU DRAMCON3Reserved:SHL:4
; dummy cycle
434 00000000 00000000
Trc3 EQU RAS2CASDelay3:SHL:7
435 00000000 00000000
Trp3 EQU RASPrechargeTime3:SHL:8
436 00000000 80000000
CAN3 EQU NoColumnAddr3:SHL:30
437 00000000 ;
438 00000000 A0070012
rDRAMCON3
EQU CAN3+DRAMEndPtr3+DRAMBasePtr3+T
rp3+Trc3+Tcp3+Tcs3+dumy3+EDO_Mode3
ARM Macro Assembler Page 18
439 00000000 ;--------------------------
440 00000000 00000001
SRAS2CASDelay3
EQU 1 ;(Trc)0=1cycle,1=2c
ycle
441 00000000 00000001
SRASPrechargeTime3
EQU 1 ;(Trp)0=1cycle ~ 3=
4clcyle
442 00000000 00000000
SNoColumnAddr3
EQU 0 ;0=8bit,1=9bit,2=10
bit,3=11bits
443 00000000 00000000
SCAN3 EQU SNoColumnAddr3:SHL:30
444 00000000 00000080
STrc3 EQU SRAS2CASDelay3:SHL:7
445 00000000 00000100
STrp3 EQU SRASPrechargeTime3:SHL:8
446 00000000 ;
447 00000000 00000000
rSDRAMCON3
EQU 0x00
448 00000000 ;rSDRAMCON3 EQU SCAN3+DRAMEndPtr3+DRAMBasePtr3+STrp3+
STrc3
449 00000000 ;-------------------------------------------------------
------
450 00000000
451 00000000 ;/* -> REFEXTCON : External I/O & Memory Refresh cycle C
ontrol Register */
452 00000000 ;-------------------------------------------------------
------
453 00000000 00000010
RefCycle
EQU 16 ;Unit [us], 1k refr
esh 16ms
454 00000000 ;RefCycle EQU 8 ;Unit [us], 1k refresh 16ms
455 00000000 00000000
CASSetupTime
EQU 0 ;0=1cycle, 1=2cycle
456 00000000 00000000
CASHoldTime
EQU 0 ;0=1cycle, 1=2cycle
, 2=3cycle,
457 00000000 ;3=4cycle, 4=5cycle,
458 00000000 9C200000
RefCycleValue
EQU ((2048+1-(RefCycle*fMCLK)):SHL:
21)
459 00000000 00000000
Tcsr EQU (CASSetupTime:SHL:20) ; 1cycle
460 00000000 00000000
Tcs EQU (CASHoldTime:SHL:17)
461 00000000 00018360
ExtIOBase
EQU 0x18360 ; Refresh enable, V
SF=1
462 00000000 ;
ARM Macro Assembler Page 19
463 00000000 9C218360
rREFEXTCON
EQU RefCycleValue+Tcsr+Tcs+ExtIOBas
e
464 00000000 ;-------------------------------------------------------
------
465 00000000 ;SRefCycle EQU 16 ;Unit [us], 4k refresh 64ms
466 00000000 00000008
SRefCycle
EQU 8 ;Unit [us], 4k refr
esh 64ms
467 00000000 00000003
ROWcycleTime
EQU 3 ;0=1cycle, 1=2cycle
, 2=3cycle,
468 00000000 ;3=4cycle, 4=5cycle,
469 00000000 CE200000
SRefCycleValue
EQU ((2048+1-(SRefCycle*fMCLK)):SHL
:21)
470 00000000 00060000
STrc EQU (ROWcycleTime:SHL:17)
471 00000000 CE278360
rSREFEXTCON
EQU SRefCycleValue+STrc+ExtIOBase
472 00000000 ;-------------------------------------------------------
------
473 00000000
474 00000000
475 00000000 ;/******************************************************
*********/
476 00000000 END
17 00000000
18 00000000 ENTRY
19 00000000
20 00000000 ;disable interrupts in CPU and switch to SVC32 mode
21 00000000 start
22 00000000 E10F0000 MRS r0, cpsr
23 00000004 E3C0003F BIC r0, r0, #MASK_MODE
24 00000008 E3800013 ORR r0, r0, #MODE_SVC32
25 0000000C E3800080 ORR r0, r0, #I_BIT
26 00000010 E3800040 ORR r0, r0, #F_BIT
27 00000014 E121F000 MSR cpsr_c, r0
28 00000018 ;disable individual interrupts in the interrupt controll
er
29 00000018
30 00000018 E59F2060 LDR r2, =ARM7_INTMASK ;R2->interrup
t controller
31 0000001C E3E01000 MVN r1, #0 ;&FFFFFFFF
32 00000020 E5821000 STR r1, [r2] ;disable all interr
upt soucres
33 00000024
34 00000024 E59F2058 LDR r2, =ARM7_INTPEND ;R2->interrup
t pend register.
35 00000028 E3E01000 MVN r1, #0 ;&FFFFFFFF
36 0000002C E5821000 STR r1, [r2] ;clear all interrup
t flags.
37 00000030
38 00000030 SYNC_DRAM
ARM Macro Assembler Page 20
39 00000030 E59F0050 LDR r0, =ARM7_SYSCFG
40 00000034 E59F1050 LDR r1, =0x87ffff90 ;config syscofi
g register.
41 00000038 E5801000 STR r1, [r0] ;Cache,WB disable
42 0000003C
43 0000003C ;ROM and RAM Configuration(Multiple Load and Store). Mu
ltiple load
44 0000003C ;LDMIA instruction cannot be used as there is no way to
load the
45 0000003C ;address L$_SystemInitDataSDRAM into a register (LDR Rn,
=sym is broken)
46 0000003C
47 0000003C
48 0000003C E59F104C LDR r1, =rEXTDBWTH ;根据snd100.h中⌨️ 快捷键说明
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