📄 init.lst
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EQU (ASIC_BASE+0x4000)
128 00000000 ;SYSTEM MANAGER REGISTERS
129 00000000
130 00000000 03FF0000
ARM7_SYSCFG
EQU (ASIC_BASE+0x0000)
131 00000000 03FF3000
ARM7_CLKCON
EQU (ASIC_BASE+0x3000)
132 00000000 03FF3008
ARM7_EXTACON0
ARM Macro Assembler Page 6
EQU (ASIC_BASE+0x3008)
133 00000000 03FF300C
ARM7_EXTACON1
EQU (ASIC_BASE+0x300c)
134 00000000 03FF3010
ARM7_EXTDBWTH
EQU (ASIC_BASE+0x3010)
135 00000000 03FF3014
ARM7_ROMCON0
EQU (ASIC_BASE+0x3014)
136 00000000 03FF3018
ARM7_ROMCON1
EQU (ASIC_BASE+0x3018)
137 00000000 03FF301C
ARM7_ROMCON2
EQU (ASIC_BASE+0x301c)
138 00000000 03FF3020
ARM7_ROMCON3
EQU (ASIC_BASE+0x3020)
139 00000000 03FF3024
ARM7_ROMCON4
EQU (ASIC_BASE+0x3024)
140 00000000 03FF3028
ARM7_ROMCON5
EQU (ASIC_BASE+0x3028)
141 00000000 03FF302C
ARM7_DRAMCON0
EQU (ASIC_BASE+0x302c)
142 00000000 03FF3030
ARM7_DRAMCON1
EQU (ASIC_BASE+0x3030)
143 00000000 03FF3034
ARM7_DRAMCON2
EQU (ASIC_BASE+0x3034)
144 00000000 03FF3038
ARM7_DRAMCON3
EQU (ASIC_BASE+0x3038)
145 00000000 03FF303C
ARM7_REFEXTCON
EQU (ASIC_BASE+0x303c)
146 00000000
147 00000000 ; controller registers
148 00000000 03FF4000
ARM7_INTMODE
EQU (ASIC_BASE+0x4000)
149 00000000 03FF4004
ARM7_INTPEND
EQU (ASIC_BASE+0x4004)
150 00000000 03FF4008
ARM7_INTMASK
EQU (ASIC_BASE+0x4008)
151 00000000 03FF4024
ARM7_INTOFFSET
EQU (ASIC_BASE+0x4024)
152 00000000 03FF402C
ARM7_INTPENDTST
EQU (ASIC_BASE+0x402c)
153 00000000
154 00000000 001FFFFF
ARM Macro Assembler Page 7
INT_DISABLE
EQU 0x1fffff
155 00000000
156 00000000 03FF400C
ARM7_INTPRI0
EQU (ASIC_BASE+0x400C)
157 00000000 03FF4010
ARM7_INTPRI1
EQU (ASIC_BASE+0x4010)
158 00000000 03FF4014
ARM7_INTPRI2
EQU (ASIC_BASE+0x4014)
159 00000000 03FF4018
ARM7_INTPRI3
EQU (ASIC_BASE+0x4018)
160 00000000 03FF401C
ARM7_INTPRI4
EQU (ASIC_BASE+0x401C)
161 00000000 03FF4020
ARM7_INTPRI5
EQU (ASIC_BASE+0x4020)
162 00000000
163 00000000 03FF4030
ARM7_INTOSET_FIQ
EQU (ASIC_BASE+0x4030)
164 00000000 03FF4034
ARM7_INTOSET_IRQ
EQU (ASIC_BASE+0x4034)
165 00000000
166 00000000 ; I/O Port Interface
167 00000000
168 00000000 03FF5000
ARM7_IOPMOD
EQU (ASIC_BASE+0x5000)
169 00000000 03FF5004
ARM7_IOPCON
EQU (ASIC_BASE+0x5004)
170 00000000 03FF5008
ARM7_IOPDATA
EQU (ASIC_BASE+0x5008)
171 00000000
172 00000000 ; IIC Registers
173 00000000 03FFF000
ARM7_IICCON
EQU (ASIC_BASE+0xf000)
174 00000000 03FFF004
ARM7_IICBUF
EQU (ASIC_BASE+0xf004)
175 00000000 03FFF008
ARM7_IICPS
EQU (ASIC_BASE+0xf008)
176 00000000 03FFF00C
ARM7_IICCNT
EQU (ASIC_BASE+0xf00c)
177 00000000
178 00000000 00000000
RESET_ROM_START
EQU 0x0
179 00000000 00040000
ARM Macro Assembler Page 8
ROM_COPY_SIZE
EQU 0x40000 ;256K
180 00000000 01000000
RESET_DRAM_START
EQU 0x1000000 ;16M
181 00000000
182 00000000
183 00000000 ;/******************************************************
*******************/
184 00000000 ;/* SYSTEM MEMORY CONTROL REGISTER EQU TABLES
*/
185 00000000 ;/******************************************************
*******************/
186 00000000 ;
187 00000000 ;/* -> EXTDBWTH : Memory Bus Width register */
188 00000000 ;-------------------------------------------------------
------
189 00000000 ;
190 00000000 00000001
DSR0 EQU 1:SHL:0 ; ROM0, 0 : Disable
191 00000000 ; 1 : Byte
192 00000000 ; 2 : Half-Word
193 00000000 ; 3 : Word
194 00000000 00000008
DSR1 EQU 2:SHL:2 ; ROM1
195 00000000 00000000
DSR2 EQU 0:SHL:4 ; ROM2
196 00000000 00000000
DSR3 EQU 0:SHL:6 ; ROM3
197 00000000 00000000
DSR4 EQU 0:SHL:8 ; ROM4
198 00000000 00000000
DSR5 EQU 0:SHL:10 ; ROM5
199 00000000 00003000
DSD0 EQU 3:SHL:12 ; DRAM0
200 00000000 00000000
DSD1 EQU 0:SHL:14 ; DRAM1
201 00000000 00000000
DSD2 EQU 0:SHL:16 ; DRAM2
202 00000000 00000000
DSD3 EQU 0:SHL:18 ; DRAM3
203 00000000 00000000
DSX0 EQU 0:SHL:20 ; EXTIO0
204 00000000 00000000
DSX1 EQU 0:SHL:22 ; EXTIO1
205 00000000 00000000
DSX2 EQU 0:SHL:24 ; EXTIO2
206 00000000 00000000
DSX3 EQU 0:SHL:26 ; EXTIO3
207 00000000
208 00000000 00003009
rEXTDBWTH
EQU DSR0+DSR1+DSR2+DSR3+DSR4+DSR5+D
SD0+DSD1+DSD2+DSD3+DSX0+DSX1+DSX2+DSX3
209 00000000 ;-------------------------------------------------------
------
210 00000000
211 00000000 ;/* -> ROMCON0 : ROM Bank0 Control register */
ARM Macro Assembler Page 9
212 00000000 ;-------------------------------------------------------
------
213 00000000 00000000
ROMBasePtr0
EQU 0x000:SHL:10 ;=0x0000000
214 00000000 01000000
ROMEndPtr0
EQU 0x010:SHL:20 ;=0x0100000
215 00000000 00000000
PMC0 EQU 0x0 ; 0x0=Normal ROM, 0
x1=4Word Page
216 00000000 ; 0x2=8Word Page, 0x3=16Word Page
217 00000000 00000000
rTpa0 EQU (0x0:SHL:2) ; 0x0=5Cycle, 0x1=2
Cycle
218 00000000 ; 0x2=3Cycle, 0x3=4Cycle
219 00000000 00000060
rTacc0 EQU (0x6:SHL:4) ; 0x0=Disable, 0x1=
2Cycle
220 00000000 ; 0x2=3Cycle, 0x3=4Cycle
221 00000000 ; 0x4=5Cycle, 0x5=6Cycle
222 00000000 ; 0x6=7Cycle, 0x7=Reserved
223 00000000 01000060
rROMCON0
EQU ROMEndPtr0+ROMBasePtr0+rTacc0+r
Tpa0+PMC0
224 00000000 ;-------------------------------------------------------
------
225 00000000
226 00000000 ;-------------------------------------------------------
------
227 00000000
228 00000000 ;/* -> ROMCON0 : ROM Bank0 Control register remap set */
229 00000000 ;-------------------------------------------------------
------
230 00000000 00040000
ROMBasePtr0_S
EQU 0x100:SHL:10 ;=0x1000000 16M
231 00000000 11000000
ROMEndPtr0_S
EQU 0x110:SHL:20 ;=0x1100000 17M
232 00000000 11040060
rROMCON0_S
EQU ROMBasePtr0_S+ROMEndPtr0_S+rTac
c0+rTpa0+PMC0
233 00000000 ;-------------------------------------------------------
------
234 00000000
235 00000000
236 00000000
237 00000000 ;/* -> ROMCON1 : ROM Bank1 Control register */
238 00000000 ;-------------------------------------------------------
------
239 00000000 00044000
ROMBasePtr1
EQU 0x110:SHL:10 ;=0x1100000 17M
240 00000000 13000000
ROMEndPtr1
ARM Macro Assembler Page 10
EQU 0x130:SHL:20 ;=0x1300000 19M
241 00000000 00000000
PMC1 EQU 0x0 ; 0x0=Normal ROM, 0
x1=4Word Page
242 00000000 ; 0x2=8Word Page, 0x3=16Word Page
243 00000000 00000000
rTpa1 EQU (0x0:SHL:2) ; 0x0=5Cycle, 0x1=2
Cycle
244 00000000 ; 0x2=3Cycle, 0x3=4Cycle
245 00000000 00000060
rTacc1 EQU (0x6:SHL:4) ; 0x0=Disable, 0x1=
2Cycle
246 00000000 ; 0x2=3Cycle, 0x3=4Cycle
247 00000000 ; 0x4=5Cycle, 0x5=6Cycle
248 00000000 ; 0x6=7Cycle, 0x7=Reserved
249 00000000 13044060
rROMCON1
EQU ROMEndPtr1+ROMBasePtr1+rTacc1+r
Tpa1+PMC1
250 00000000 ;-------------------------------------------------------
------
251 00000000
252 00000000 ;/* -> ROMCON2 : ROM Bank2 Control register */
253 00000000 ;-------------------------------------------------------
------
254 00000000 00010000
ROMBasePtr2
EQU 0x040:SHL:10 ;=0x0400000
255 00000000 06000000
ROMEndPtr2
EQU 0x060:SHL:20 ;=0x0600000
256 00000000 00000000
PMC2 EQU 0x0 ; 0x0=Normal ROM, 0
x1=4Word Page
257 00000000 ; 0x2=8Word Page, 0x3=16Word Page
258 00000000 00000000
rTpa2 EQU (0x0:SHL:2) ; 0x0=5Cycle, 0x1=2
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