📄 snds.lst
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298 00000000 ;rROMCON4 EQU ROMEndPtr4+ROMBasePtr4+rTacc4+rTpa4+PMC
4
299 00000000 ;-------------------------------------------------------
------
300 00000000
301 00000000 ;/* -> ROMCON5 : ROM Bank5 Control register */
302 00000000 ;-------------------------------------------------------
------
303 00000000 00028000
ROMBasePtr5
EQU 0x0A0:SHL:10 ;=0x0A00000
304 00000000 0C000000
ROMEndPtr5
EQU 0x0C0:SHL:20 ;=0x0C00000
305 00000000 00000000
PMC5 EQU 0x0 ; 0x0=Normal ROM, 0
x1=4Word Page
306 00000000 ; 0x2=8Word Page, 0x3=16Word Page
307 00000000 00000000
rTpa5 EQU (0x0:SHL:2) ; 0x0=5Cycle, 0x1=2
Cycle
308 00000000 ; 0x2=3Cycle, 0x3=4Cycle
309 00000000 00000040
rTacc5 EQU (0x4:SHL:4) ; 0x0=Disable, 0x1=
2Cycle
310 00000000 ; 0x2=3Cycle, 0x3=4Cycle
311 00000000 ; 0x4=5Cycle, 0x5=6Cycle
ARM Macro Assembler Page 12
312 00000000 ; 0x6=7Cycle, 0x7=Reserved
313 00000000 00000060
rROMCON5
EQU 0x60
314 00000000 ;rROMCON5 EQU ROMEndPtr5+ROMBasePtr5+rTacc5+rTpa5+PMC
5
315 00000000 ;-------------------------------------------------------
------
316 00000000
317 00000000
318 00000000 ;/* -> DRAMCON0 : RAM Bank0 control register */
319 00000000 ;-------------------------------------------------------
------
320 00000000 00000001
EDO_Mode0
EQU 1 ;(EDO)0=Normal, 1=E
DO DRAM
321 00000000 00000000
CasPrechargeTime0
EQU 0 ;(Tcp)0=1cycle,1=2c
ycle
322 00000000 00000001
CasStrobeTime0
EQU 1 ;(Tcs)0=1cycle ~ 3=
4cycle
323 00000000 00000001
DRAMCON0Reserved
EQU 1 ; Must be set to 1
324 00000000 00000000
RAS2CASDelay0
EQU 0 ;(Trc)0=1cycle,1=2c
ycle
325 00000000 00000002
RASPrechargeTime0
EQU 2 ;(Trp)0=1cycle ~ 3=
4clcyle
326 00000000 00004000
DRAMBasePtr0
EQU 0x10:SHL:10 ;=0x00100000 1M
327 00000000 11000000
DRAMEndPtr0
EQU 0x110:SHL:20 ;=0x01100000 17M
328 00000000 00000002
NoColumnAddr0
EQU 2 ;0=8bit,1=9bit,2=10
bit,3=11bits
329 00000000 ;-------------------------------------------------------
------
330 00000000 00000002
Tcs0 EQU CasStrobeTime0:SHL:1
331 00000000 00000000
Tcp0 EQU CasPrechargeTime0:SHL:3
332 00000000 00000010
dumy0 EQU DRAMCON0Reserved:SHL:4
; dummy cycle
333 00000000 00000000
Trc0 EQU RAS2CASDelay0:SHL:7
334 00000000 00000200
ARM Macro Assembler Page 13
Trp0 EQU RASPrechargeTime0:SHL:8
335 00000000 80000000
CAN0 EQU NoColumnAddr0:SHL:30
336 00000000 ;
337 00000000 91004213
rDRAMCON0
EQU CAN0+DRAMEndPtr0+DRAMBasePtr0+T
rp0+Trc0+Tcp0+Tcs0+dumy0+EDO_Mode0
338 00000000 ;-------------------------------------------------------
---------------------------
339 00000000 00000001
SRAS2CASDelay0
EQU 1 ;(Trc)0=1cycle,1=2c
ycle
340 00000000 00000003
SRASPrechargeTime0
EQU 3 ;(Trp)0=1cycle ~ 3=
4clcyle
341 00000000 00000000
SNoColumnAddr0
EQU 0 ;0=8bit,1=9bit,2=10
bit,3=11bits
342 00000000 00000000
SCAN0 EQU SNoColumnAddr0:SHL:30
343 00000000 00000080
STrc0 EQU SRAS2CASDelay0:SHL:7
344 00000000 00000300
STrp0 EQU SRASPrechargeTime0:SHL:8
345 00000000 ;
346 00000000 11004380
rSDRAMCON0
EQU SCAN0+DRAMEndPtr0+DRAMBasePtr0+
STrp0+STrc0
;+dumy0
347 00000000 ;/* -> DRAMCON0 : RAM Bank0 control register remap */
348 00000000 ;-------------------------------------------------------
------
349 00000000
350 00000000 00000000
DRAMBasePtr0_S
EQU 0x000:SHL:10 ;=0x1000000 0M
351 00000000 10000000
DRAMEndPtr0_S
EQU 0x100:SHL:20 ;=0x2000000 16M
352 00000000 10000380
rSDRAMCON0_S
EQU SCAN0+DRAMEndPtr0_S+DRAMBasePtr
0_S+STrp0+STrc0
353 00000000
354 00000000
355 00000000 ;/* -> DRAMCON1 : RAM Bank1 control register */
356 00000000 ;-------------------------------------------------------
------
357 00000000 00000001
EDO_Mode1
EQU 1 ;(EDO)0=Normal, 1=E
DO DRAM
358 00000000 00000000
CasPrechargeTime1
ARM Macro Assembler Page 14
EQU 0 ;(Tcp)0=1cycle,1=2c
ycle
359 00000000 00000001
CasStrobeTime1
EQU 1 ;(Tcs)0=1cycle ~ 3=
4cycle
360 00000000 00000000
DRAMCON1Reserved
EQU 0 ; Must be set to 1
361 00000000 00000000
RAS2CASDelay1
EQU 0 ;(Trc)0=1cycle,1=2c
ycle
362 00000000 00000000
RASPrechargeTime1
EQU 0 ;(Trp)0=1cycle ~ 3=
4clcyle
363 00000000 00050000
DRAMBasePtr1
EQU 0x140:SHL:10 ;=0x14000000
364 00000000 18000000
DRAMEndPtr1
EQU 0x180:SHL:20 ;=0x18000000
365 00000000 00000002
NoColumnAddr1
EQU 2 ;0=8bit,1=9bit,2=10
bit,3=11bits
366 00000000 ;-------------------------------------------------------
------
367 00000000 00000002
Tcs1 EQU CasStrobeTime1:SHL:1
368 00000000 00000000
Tcp1 EQU CasPrechargeTime1:SHL:3
369 00000000 00000000
dumy1 EQU DRAMCON1Reserved:SHL:4
; dummy cycle
370 00000000 00000000
Trc1 EQU RAS2CASDelay1:SHL:7
371 00000000 00000000
Trp1 EQU RASPrechargeTime1:SHL:8
372 00000000 80000000
CAN1 EQU NoColumnAddr1:SHL:30
373 00000000 ;
374 00000000 98050003
rDRAMCON1
EQU CAN1+DRAMEndPtr1+DRAMBasePtr1+T
rp1+Trc1+Tcp1+Tcs1+dumy1+EDO_Mode1
375 00000000 ;-------------------------------------------------------
---------------------------
376 00000000 00000001
SRAS2CASDelay1
EQU 1 ;(Trc)0=1cycle,1=2c
ycle
377 00000000 00000001
SRASPrechargeTime1
EQU 1 ;(Trp)0=1cycle ~ 3=
4clcyle
378 00000000 00000000
SNoColumnAddr1
ARM Macro Assembler Page 15
EQU 0 ;0=8bit,1=9bit,2=10
bit,3=11bits
379 00000000 00000000
SCAN1 EQU SNoColumnAddr1:SHL:30
380 00000000 00000080
STrc1 EQU SRAS2CASDelay1:SHL:7
381 00000000 00000100
STrp1 EQU SRASPrechargeTime1:SHL:8
382 00000000 ;
383 00000000 00000000
rSDRAMCON1
EQU 0x00
384 00000000 ;rSDRAMCON1 EQU SCAN1+DRAMEndPtr1+DRAMBasePtr1+STrp1+
STrc1
385 00000000 ;-------------------------------------------------------
------
386 00000000
387 00000000 ;/* -> DRAMCON2 : RAM Bank2 control register */
388 00000000 ;-------------------------------------------------------
------
389 00000000 00000000
EDO_Mode2
EQU 0 ;(EDO)0=Normal, 1=E
DO DRAM
390 00000000 00000000
CasPrechargeTime2
EQU 0 ;(Tcp)0=1cycle,1=2c
ycle
391 00000000 00000001
CasStrobeTime2
EQU 1 ;(Tcs)0=1cycle ~ 3=
4cycle
392 00000000 00000001
DRAMCON2Reserved
EQU 1 ; Must be set to 1
393 00000000 00000000
RAS2CASDelay2
EQU 0 ;(Trc)0=1cycle,1=2c
ycle
394 00000000 00000000
RASPrechargeTime2
EQU 0 ;(Trp)0=1cycle ~ 3=
4clcyle
395 00000000 00060000
DRAMBasePtr2
EQU 0x180:SHL:10 ;=0x14000000
396 00000000 1C000000
DRAMEndPtr2
EQU 0x1C0:SHL:20 ;=0x18000000
397 00000000 00000002
NoColumnAddr2
EQU 2 ;0=8bit,1=9bit,2=10
bit,3=11bits
398 00000000 ;-------------------------------------------------------
------
399 00000000 00000002
Tcs2 EQU CasStrobeTime2:SHL:1
400 00000000 00000000
Tcp2 EQU CasPrechargeTime2:SHL:3
ARM Macro Assembler Page 16
401 00000000 00000010
dumy2 EQU DRAMCON2Reserved:SHL:4
; dummy cycle
402 00000000 00000000
Trc2 EQU RAS2CASDelay2:SHL:7
403 00000000 00000000
Trp2 EQU RASPrechargeTime2:SHL:8
404 00000000 80000000
CAN2 EQU NoColumnAddr2:SHL:30
405 00000000 ;
406 00000000 9C060012
rDRAMCON2
EQU CAN2+DRAMEndPtr2+DRAMBasePtr2+T
rp2+Trc2+Tcp2+Tcs2+dumy2+EDO_Mode2
407 00000000 ;--------------------------
408 00000000 00000001
SRAS2CASDelay2
EQU 1 ;(Trc)0=1cycle,1=2c
ycle
409 00000000 00000001
SRASPrechargeTime2
EQU 1 ;(Trp)0=1cycle ~ 3=
4clcyle
410 00000000 00000000
SNoColumnAddr2
EQU 0 ;0=8bit,1=9bit,2=10
bit,3=11bits
411 00000000 00000000
SCAN2 EQU SNoColumnAddr2:SHL:30
412 00000000 00000080
STrc2 EQU SRAS2CASDelay2:SHL:7
413 00000000 00000100
STrp2 EQU SRASPrechargeTime2:SHL:8
414 00000000 ;
415 00000000 00000000
rSDRAMCON2
EQU 0x00
416 00000000 ;rSDRAMCON2 EQU SCAN2+DRAMEndPtr2+DRAMBasePtr2+STrp2+
STrc2
417 00000000 ;-------------------------------------------------------
------
418 00000000
419 00000000 ;/* -> DRAMCON3 : RAM Bank3 control register */
420 00000000 ;-------------------------------------------------------
------
421 00000000 00000000
EDO_Mode3
EQU 0 ;(EDO)0=Normal, 1=E
DO DRAM
422 00000000 00000000
CasPrechargeTime3
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