dm9000x.c

S3C2440开发板

/*
  dm9000x.c: Version 1.25 04/28/2004
  
        A Davicom DM9000 ISA NIC fast Ethernet driver for Linux.
	Copyright (C) 1997  Sten Wang

	This program is free software; you can redistribute it and/or
	modify it under the terms of the GNU General Public License
	as published by the Free Software Foundation; either version 2
	of the License, or (at your option) any later version.

	This program is distributed in the hope that it will be useful,
	but WITHOUT ANY WARRANTY; without even the implied warranty of
	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
	GNU General Public License for more details.

  (C)Copyright 1997-1998 DAVICOM Semiconductor,Inc. All Rights Reserved.

V0.11	06/20/2001	REG_0A bit3=1, default enable BP with DA match
	06/22/2001 	Support DM9801 progrmming	
	 	 	E3: R25 = ((R24 + NF) & 0x00ff) | 0xf000
		 	E4: R25 = ((R24 + NF) & 0x00ff) | 0xc200
		     		R17 = (R17 & 0xfff0) | NF + 3
		 	E5: R25 = ((R24 + NF - 3) & 0x00ff) | 0xc200
		     		R17 = (R17 & 0xfff0) | NF
				
v1.00               	modify by simon 2001.9.5
                        change for kernel 2.4.x    
			
v1.1   11/09/2001      	fix force mode bug             

v1.2   03/18/2003       Weilun Huang <[e-mail]>:
			Added tx/rx 32 bit mode.
			Cleaned up for kernel merge.
			
v1.21  08/26/2003       Fixed phy reset.

v1.22  09/09/2003       Fixed power-on reset.
       09/30/2003	Spenser Tsai
			Fixed 32-bit mode bug (Excessive Collision and Late Collision)

v1.23  11/05/2003	Added Auto-MDIX function
v1.24  01/15/2004	Modify Full-Duplex mode
v1.25  04/28/2004	Default Flow control function
v1.26 06/09/2004	Performance raising & reducing amount of interrupt 
*/
//modified by ucdragon_fla,the major to do is configureing cs and interrupt base certian board!

#if defined(MODVERSIONS)
#include <linux/modversions.h>
#endif

#include <linux/module.h>
#include <linux/version.h>
#include <linux/netdevice.h>
#include <linux/etherdevice.h>
#include <linux/spinlock.h>
#include <linux/skbuff.h>
#include <linux/ioport.h>
#include <linux/crc32.h>
#include <linux/delay.h>
#include <asm/dma.h>
#include <asm/irq.h>
#include <asm/arch/hardware.h>
#include <asm/arch/regs-gpio.h>
#include <asm/io.h>

////#include <asm-arm/arch-s3c2410/s3c2410.h> //--
#include <asm-arm/arch/irqs.h> //--
//#include "asm/arch/smdk2410.h" //--
#include "dm9000.h"
#include <linux/mii.h>

//SUN ADD
static void *bwscon;
static void *gpfcon,*gpfcon1;
static void *extint0,*extint01;
static void *intmsk;
#define BWSCON           (0x48000000)
#define GPFCON           (0x56000060)  //infact: GPGCON=0X56000060
#define GPFCON1          (0x56000050)
//#define EXTINT0           (0x56000088)
#define EXTINT0          (0x5600008C)                 //fla in fact :EXTINT1=0X5600008C
#define EXTINT01         (0x56000088)
#define INTMSK           (0x4A000008)
//////

#define	IRQ_LAN_ETH		10
#ifdef	CONFIG_HHBF
#include <asm/blackfin.h>

#ifdef	CONFIG_BF561
#undef	pSIC_ISR
#define	pSIC_ISR		pSICA_ISR1
#endif	/* comment by mhfan */
#define	LAN_FIO_PATTERN		PF10



//EMU32BITFLAGS = -DEMU32
//AUTOMDIXFLAGS = -DAUTOMDIX
//HDX32BITFLAGS = -DHDX32
//#define       DM9000_DEBUG
#endif	/* comment by mhfan */

/* Board/System/Debug information/definition ---------------- */

#define DM9000_ID		0x90000A46

#define DM9000_NCR		0x00
#define DM9000_NSR		0x01
#define DM9000_REG05		0x30	/* SKIP_CRC/SKIP_LONG */
#define DM9000_REG08		0x37
#define DM9000_REG09		0x38
#define DM9000_REG0A		0x29	/* Flow Control Enable */
#define DM9000_GPCR		0x1e	/* General purpose control register */
#define DM9000_GPR		0x1f	/* General purpose register */
#define DM9000_REGFF		0x83	/* IMR */

#define DM9000_PHY		0x40	/* PHY address 0x01 */
#define DM9000_PKT_MAX		1536	/* Received packet max size */
#define DM9000_PKT_RDY		0x01	/* Packet ready to receive */



#define DM9000_MIN_IO		0x20000300 //--fla

//--fla  for u-sbc2440
#ifdef  YLE2440_BANK4	//qsm2007-05-28
#undef  DM9000_MIN_IO
#define DM9000_MIN_IO   0x18000300  //
#endif
//--end

////#define DM9000_MAX_IO		0x04000370
#define DM9000_MAX_IO	  0x20000370 //--fla


//--fla  for u-sbc2440
#ifdef  YLE2440_BANK4
#undef  DM9000_MAX_IO
#define DM9000_MAX_IO   0x18000370  //
#endif
//--end


#define DM9000_INT_MII		0x00
#define DM9000_EXT_MII		0x80

#define DM9000_VID_L		0x28
#define DM9000_VID_H		0x29
#define DM9000_PID_L		0x2A
#define DM9000_PID_H		0x2B

#define DM9801_NOISE_FLOOR	0x08
#define DM9802_NOISE_FLOOR	0x05

#define DMFE_SUCC       	0
#define MAX_PACKET_SIZE 	1514
#define DMFE_MAX_MULTICAST 	14

#define DM9000_RX_INTR		0x01
#define DM9000_TX_INTR		0x02
#define DM9000_OVERFLOW_INTR	0x04

#define DM9000_DWORD_MODE	1
#define DM9000_BYTE_MODE	2
#define DM9000_WORD_MODE	0

#define TRUE			1
#define FALSE			0

#define DMFE_TIMER_WUT  jiffies+(HZ*2)	/* timer wakeup time : 2 second */
#define DMFE_TX_TIMEOUT (HZ*2)	/* tx packet time-out time 1.5 s" */
#if defined(AUTOMDIX)
#define DMFE_TIMER_MDIX	jiffies+(HZ*1)	/* timer wakeup time : 1 second */
#endif

#if defined(DM9000_DEBUG)
#define DMFE_DBUG(dbug_now, msg, vaule)\
if (dmfe_debug||dbug_now) //printk(KERN_ERR "dmfe: %s %x\n", msg, vaule)
#else
#define DMFE_DBUG(dbug_now, msg, vaule)\
if (dbug_now) //printk(KERN_ERR "dmfe: %s %x\n", msg, vaule)
#endif

enum DM9000_PHY_mode {
    DM9000_10MHD = 0,
    DM9000_100MHD = 1,
    DM9000_10MFD = 4,
    DM9000_100MFD = 5,
    DM9000_AUTO = 8,
    DM9000_1M_HPNA = 0x10
};

enum DM9000_NIC_TYPE {
    FASTETHER_NIC = 0,
    HOMERUN_NIC = 1,
    LONGRUN_NIC = 2
};

// Active operation mode  - Spenser 10/6
enum DM9000_OP_mode {
    OP_10MHD = 1,
    OP_10MFD = 2,
    OP_100MHD = 4,
    OP_100MFD = 8
};

enum DM9000_SF_mode {
    VLAN_Enable = 1,
    FlowControl = 2,
    TxPausePacket = 4
};

/* Structure/enum declaration ------------------------------- */
typedef struct board_info {

    u32 runt_length_counter;	/* counter: RX length < 64byte */
    u32 long_length_counter;	/* counter: RX length > 1514byte */
    u32 reset_counter;		/* counter: RESET */
    u32 reset_tx_timeout;	/* RESET caused by TX Timeout */
    u32 reset_rx_status;	/* RESET caused by RX Statsus wrong */

    u32 ioaddr;			/* Register I/O base address */
#define io_addr ioaddr
    u32 io_data;		/* Data I/O address */
    u16 irq;			/* IRQ */

    u16 tx_pkt_cnt;
    u16 sent_pkt_len, queue_pkt_len;
    u16 queue_start_addr;
    u16 dbug_cnt;
    u16 Preg0;
    u16 Preg4;

    u8 reg0, reg5, reg8, reg9, rega;	/* registers saved */
    u8 op_mode;			/* PHY operation mode */
//      u8 active_op_mode;      // Real PHY operation mode -Spenser 10/6
    u8 io_mode;			/* 0:word, 2:byte */
    u8 phy_addr;
    u8 link_failed;		/* Ever link failed */
    u8 nsr;			/* Network Status Register */
    u8 link_status;		/* Detect link state */
    u8 mdix;			/* MDIX */
    u8 device_wait_reset;	/* device state */
    u8 nic_type;		/* NIC type */
    u8 ncr;

    struct timer_list timer, mdix_timer;
    struct net_device_stats stats;
//      unsigned char srom[128];
    spinlock_t lock;
    struct mii_if_info mii;
    struct semaphore addr_lock;
    u32 msg_enable;
    unsigned int in_suspend :1;
}   board_info_t;

/* Global variable declaration ----------------------------- */
#ifdef	DM9000_DEBUG
static int dmfe_debug	= 1;
#endif // DM9000_DEBUG
static struct net_device *dmfe_dev = NULL;

/* For module input parameter */
#ifdef	MODULE
static int debug	= 0;
static int mode		= DM9000_AUTO;
#endif//MODULE
static int media_mode	= DM9000_AUTO;
static u8 nfloor	= 0;
static u8 reg5		= DM9000_REG05;
static u8 reg8		= DM9000_REG08;
static u8 reg9		= DM9000_REG09;
static u8 rega		= DM9000_REG0A;

//static u8 irqline     = 3;
static u32 tintrflag	= 0;
static u32 rxintrflag	= 0;

/* function declaration ------------------------------------- */
int dmfe_probe(struct net_device *);
static int dmfe_open(struct net_device *);
static int dmfe_start_xmit(struct sk_buff *, struct net_device *);
static void dmfe_tx_done(unsigned long);
static void dmfe_packet_receive(unsigned long);
static int dmfe_stop(struct net_device *);
static struct net_device_stats *dmfe_get_stats(struct net_device *);
static int dmfe_do_ioctl(struct net_device *, struct ifreq *, int);
static int dmfe_interrupt(int, void *, struct pt_regs *);
static void dmfe_timer(unsigned long);
static void dmfe_init_dm9000(struct net_device *);

//static void dmfe_reset_dm9000(struct net_device *);
static unsigned long cal_CRC(unsigned char *, unsigned int, u8);
static u8 ior(board_info_t *, int);
static void iow(board_info_t *, int, u8);
static u16 phy_read(board_info_t *, int);
static void phy_write(board_info_t *, int, u16);

//static u16 read_srom_word(board_info_t *, int);
static void dm9000_hash_table(struct net_device *);

#if defined(AUTOMDIX)
static void dmfe_mdix_timer(unsigned long);
#endif

#if 0 	/* comment by mhfan */
DECLARE_TASKLET(dmfe_rx_tasklet, dmfe_packet_receive, 0);
DECLARE_TASKLET(dmfe_tx_tasklet, dmfe_tx_done, 0);
#endif	/* comment by mhfan */


/*
 * Sleep, either by using msleep() or if we are suspending, then
 * use mdelay() to sleep.
 */
static void dm9000_msleep(board_info_t *db, unsigned int ms)
{
	if (db->in_suspend)
		mdelay(ms);
	else
		msleep(ms);
}


/*
 *   Read a word from phyxcer
 */
static int
dm9000_phy_read(struct net_device *dev, int phy_reg_unused, int reg)
{
	board_info_t *db = (board_info_t *) dev->priv;
	unsigned long flags;
	unsigned int reg_save;
	int ret;

	up(&db->addr_lock);

	spin_lock_irqsave(&db->lock,flags);

	/* Save previous register address */
	reg_save = readb(db->io_addr);

	/* Fill the phyxcer register into REG_0C */
	iow(db, DM9000_EPAR, DM9000_PHY | reg);

	iow(db, DM9000_EPCR, 0xc);	/* Issue phyxcer read command */

	writeb(reg_save, db->io_addr);
	spin_unlock_irqrestore(&db->lock,flags);

	dm9000_msleep(db, 1);		/* Wait read complete */

	spin_lock_irqsave(&db->lock,flags);
	reg_save = readb(db->io_addr);

	iow(db, DM9000_EPCR, 0x0);	/* Clear phyxcer read command */

	/* The read data keeps on REG_0D & REG_0E */
	ret = (ior(db, DM9000_EPDRH) << 8) | ior(db, DM9000_EPDRL);

	/* restore the previous address */
	writeb(reg_save, db->io_addr);
	spin_unlock_irqrestore(&db->lock,flags);

	down(&db->addr_lock);
	return ret;
}

/*
 *   Write a word to phyxcer
 */
static void
dm9000_phy_write(struct net_device *dev, int phyaddr_unused, int reg, int value)
{
	board_info_t *db = (board_info_t *) dev->priv;
	unsigned long flags;
	unsigned long reg_save;

	up(&db->addr_lock);
	
	spin_lock_irqsave(&db->lock,flags);

	/* Save previous register address */
	reg_save = readb(db->io_addr);

	/* Fill the phyxcer register into REG_0C */
	iow(db, DM9000_EPAR, DM9000_PHY | reg);

	/* Fill the written data into REG_0D & REG_0E */
	iow(db, DM9000_EPDRL, value);
	iow(db, DM9000_EPDRH, value >> 8);

	iow(db, DM9000_EPCR, 0xa);	/* Issue phyxcer write command */

	writeb(reg_save, db->io_addr);
	spin_unlock_irqrestore(&db->lock, flags);

	dm9000_msleep(db, 1);		/* Wait write complete */

	spin_lock_irqsave(&db->lock,flags);
	reg_save = readb(db->io_addr);

	iow(db, DM9000_EPCR, 0x0);	/* Clear phyxcer write command */

	/* restore the previous address */
	writeb(reg_save, db->io_addr);

	spin_unlock_irqrestore(&db->lock, flags);
	down(&db->addr_lock);
}

/* DM9000 network baord routine ---------------------------- */
/* Search DM9000 board, allocate space and register it */
int dmfe_probe(struct net_device *dev)
{
    struct board_info *db;	/* Point a board information structure */
    int i;
    u32 id_val;
    u32 iobase;
    u16 dm9000_found = FALSE;
    
    //FLAAAAAAAAAAAAAAAAAAAAA
    //u32 iobase, _iobase;
    
    DMFE_DBUG(0, "dmfe_probe()", 0);

	

	bwscon=ioremap_nocache(BWSCON,0x0000004);
	
	gpfcon=ioremap_nocache(GPFCON,0x0000004);
	
	gpfcon1=ioremap_nocache(GPFCON1,0x0000004);
	//extint0=ioremap_nocache(EXTINT0,0x0000004);
	extint0=ioremap_nocache(EXTINT0,0x0000004);//fla
	extint01=ioremap_nocache(EXTINT01,0x0000004);//fla
	
	intmsk=ioremap_nocache(INTMSK,0x0000004);
	               
	
//qsm2007-05-28
#ifdef YLE2440_DEBUG	
	printk("BWSCON=%x\n",readl(bwscon));
	printk("GPFCON=%x\n",readl(gpfcon1));
	printk("EXTINT0=%x\n",readl(extint01));
	printk("INTMSK=%x\n",readl(intmsk));
#endif								
//important!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
	writel(readl(bwscon)|0xc0000,bwscon);
	//writel(readl(gpfcon)|0xaa,gpfcon); //old  fla
#ifdef YLE2440	
	writel(readl(gpfcon)|0x2000,gpfcon);  //GPG6 TO EINT14 modified byfla
	writel(readl(gpfcon)&0xffffefff,gpfcon);  //GPG6 TO EINT14 add by fla.
	
	writel(readl(gpfcon)|0x2000,gpfcon);  //GPG6 TO EINT14 modified byfla
	writel(readl(gpfcon)&0xffffefff,gpfcon);  //GPG6 TO EINT14 add by fla.
	
	
	 
	//writel(readl(gpfcon)|0x55,gpfcon);
	//writel(0x04|0x4,extint0);  //OLD
	   writel(readl(extint0)|0x1000000,extint0); //rising edge to high level
	   writel(readl(extint0)&0xf9ffffff,extint0);// 
	//writel(readl(intmsk)&0xfff7,intmsk);   //OLD
         //writel(readl(intmsk)&0xfffffff0,intmsk); //mask open
         //writel(readl(intmsk)&0xfffffff1,intmsk);
         writel(readl(intmsk)&0xffffffdf,intmsk);//available
#endif         
    //for u-sbc2440
	s3c2410_gpio_cfgpin(S3C2410_GPF3, S3C2410_GPF3_EINT3);   //for u-sbc2440
	writel((readl(extint01)&(~(3<<13)))|(1<<12),extint01); //eint3 high level
	writel(readl(intmsk)&(~(1<<3)),intmsk); //
	 //--end
#ifdef YLE2440	
	printk("\nBWSCON=%x\n",readl(bwscon));
	printk("GPFCON=%x\n",readl(gpfcon1));
	printk("EXTINT0=%x\n",readl(extint01));
	printk("INTMSK=%x\n",readl(intmsk));
#endif                                                                            
//////////////////////////////////////////////////////////////////////////

                                      //dmfe_probe:
iobase = ioremap(DM9000_MIN_IO,0x400);//--1 initialize intrrupt
                                      //--2 check product id
                                      //--3 initialize struct dev and pass to dmfe_dev which is net_device
                                      //that's all


#if 0
    *pFIO_FLAG_C   =  LAN_FIO_PATTERN;
    *pFIO_DIR     &= ~LAN_FIO_PATTERN;
    *pFIO_MASKB_C  =  LAN_FIO_PATTERN;
    *pFIO_MASKB_S  =  LAN_FIO_PATTERN;
    *pFIO_POLAR   &= ~LAN_FIO_PATTERN;
    *pFIO_EDGE    |=  LAN_FIO_PATTERN;
    *pFIO_BOTH    &= ~LAN_FIO_PATTERN;
    *pFIO_INEN    |=  LAN_FIO_PATTERN;
    asm __volatile__ ("ssync;");
#endif	/* comment by mhfan */
//modify by heA

/*  //--
   GEDR2 = 0x40000000;


        ICMR = ICMR | 0x00000400;

	GEDR2 = 0x40000000;

        GPDR2 = GPDR2 &0xbfffffff;

        GRER2 = GRER2 | 0x40000000;

	GAFR2_U = GAFR2_U & 0xcfffffff;

	//irq handle
	ICLR = ICLR & 0xfffffbff;

	//msc0

	MSC0 = MSC0 & 0x000fffff;

       MSC0 = MSC0 | 0x7ff00000;
*/
//modify by he


    /* Search All DM9000 NIC */
    do {
	outb(DM9000_VID_L, iobase);
	id_val = inb(iobase + 4);
	outb(DM9000_VID_H, iobase);
	id_val |= inb(iobase + 4) << 8;
	outb(DM9000_PID_L, iobase);