sysgei82543end.c

vxworks 834x的BSP

/* sysGei82543End.c - Intel Pro1000 F/T Adapter END driver support routines */

/*
 * Copyright (c) 2005 Wind River Systems, Inc.
 *
 * The right to copy, distribute, modify or otherwise make use
 * of this software may be licensed only pursuant to the terms
 * of an applicable Wind River license agreement.
 */


/*
modification history
--------------------
01a,25jul05,j_b  adapted from ads834x rev 01a
*/

/*
This module is BSP support for Intel PRO1000 F/T adaptors.

SEE ALSO: ifLib,
.I "RS82543GC GIGABIT ETHERNET CONTROLLER NETWORKING SILICON DEVELOPER'S MANUAL"
*/

#include <vxWorks.h>
#include <taskLib.h>
#include <sysLib.h>
#include "config.h"
#include <end.h>
#include <vmLib.h>
#include <drv/pci/pciIntLib.h>
#include <drv/end/gei82543End.h>

#if (defined(INCLUDE_GEI_END) && defined (INCLUDE_NETWORK) &&  \
     defined (INCLUDE_END))

#ifdef I82543_DEBUG
#  undef    LOCAL
#  define   LOCAL
#endif    /* I82543_DEBUG */

/* include PCI Library */

#ifndef INCLUDE_PCI
#  define INCLUDE_PCI
#endif /* INCLUDE_PCI */

/* Default RX descriptor  */

#ifndef GEI_RXDES_NUM
#  define GEI_RXDES_NUM              GEI_DEFAULT_RXDES_NUM
#endif

/* Default TX descriptor  */

#ifndef GEI_TXDES_NUM
#  define GEI_TXDES_NUM              GEI_DEFAULT_TXDES_NUM
#endif

/* Default User's flags  */

#ifndef GEI_USR_FLAG
#  define GEI_USR_FLAG               GEI_DEFAULT_USR_FLAG
#endif

/* PCI device ID for Intel 82543/82544 Ethernet */

#define PRO1000_543_PCI_DEVICE_ID_T     (0x1001) /* Copper */
#define PRO1000_543_PCI_DEVICE_ID_FT    (0x1004) /* Fiber / Copper */
#define PRO1000_544_PCI_DEVICE_ID_XT    (0x1008) /* Copper */
#define PRO1000_544_PCI_DEVICE_ID_XF    (0x1009) /* Fiber */
#define PRO1000_544_PCI_DEVICE_ID_GC    (0x100c) /* Copper */
#define PRO1000_540_PCI_DEVICE_ID_XT    (0x100e) /* Copper only */
#define PRO1000_545_PCI_DEVICE_ID_XT    (0x100f) /* Copper */
#define PRO1000_546_PCI_DEVICE_ID_XT    (0x1010) /* Copper - 82546 EB */
#define PRO1000_545_PCI_DEVICE_ID_MF    (0x1011) /* Fiber */
#define PRO1000_546_PCI_DEVICE_ID_MF    (0x1012) /* Fiber */
#define PRO1000_546_PCI_DEVICE_ID_XT2   (0x1079) /* Copper - 82546 GB */


#define GEI0_MEMBASE0_LOW           0x90000000    /* mem base for CSR */
#define GEI0_MEMBASE0_HIGH          0x00000000    /* mem base for CSR */
#define GEI0_MEMSIZE0               0x20000       /* mem size - CSR,128KB */
#define GEI0_MEMBASE1               0x00000000    /* mem base - Flash */
#define GEI0_MEMSIZE1               0x00000000    /* mem size - Flash,512KB */
#define GEI0_INT_LVL                INUM_IRQ0          /* IRQ 0 */
#define GEI0_INIT_STATE_MASK        (VM_STATE_MASK_FOR_ALL)
#define GEI0_INIT_STATE             (VM_STATE_FOR_PCI)
#define GEI0_SHMEM_BASE             NONE
#define GEI0_SHMEM_SIZE             0
#define GEI0_RXDES_NUM              GEI_RXDES_NUM
#define GEI0_TXDES_NUM              GEI_TXDES_NUM
#define GEI0_USR_FLAG               GEI_USR_FLAG


#define GEI82543_LOAD_FUNC          gei82543EndLoad
#define GEI_X86_OFFSET_VALUE        0x0

/* INTEL 82544 INTERNAL PHY */
#define INTEL_82544PHY_OUI_ID                   (0x5043)
#define INTEL_82544PHY_MODEL                    (0x3)

#define INTEL_82544PHY_PHY_SPEC_CTRL_REG        (0x10)
#define INTEL_82544PHY_PHY_SPEC_STAT_REG        (0x11)
#define INTEL_82544PHY_INT_ENABLE_REG           (0x12)
#define INTEL_82544PHY_INT_STATUS_REG           (0x13)
#define INTEL_82544PHY_EXT_PHY_SPEC_CTRL_REG    (0x14)
#define INTEL_82544PHY_RX_ERROR_COUNTER         (0x15)
#define INTEL_82544PHY_PHY_GLOBAL_STAT          (0x17)
#define INTEL_82544PHY_LED_CTRL_REG             (0x18)

#define INTEL_82544PHY_PSCR_ASSERT_CRS_ON_TX    (0x0800)
#define INTEL_82544PHY_EPSCR_TX_CLK_25          (0x0070)


/* Alaska PHY's information */

#define MARVELL_OUI_ID                  0x5043
#define MARVELL_ALASKA_88E1000          0x5
#define MARVELL_ALASKA_88E1000S         0x4
#define ALASKA_PHY_SPEC_CTRL_REG        0x10
#define ALASKA_PHY_SPEC_STAT_REG        0x11
#define ALASKA_INT_ENABLE_REG           0x12
#define ALASKA_INT_STATUS_REG           0x13
#define ALASKA_EXT_PHY_SPEC_CTRL_REG    0x14
#define ALASKA_RX_ERROR_COUNTER         0x15
#define ALASKA_LED_CTRL_REG             0x18

#define ALASKA_PSCR_ASSERT_CRS_ON_TX    0x0800
#define ALASKA_EPSCR_TX_CLK_25          0x0070

#define ALASKA_PSCR_AUTO_X_1000T        0x0040
#define ALASKA_PSCR_AUTO_X_MODE         0x0060

#define ALASKA_PSSR_DPLX                0x2000
#define ALASKA_PSSR_SPEED               0xC000
#define ALASKA_PSSR_10MBS               0x0000
#define ALASKA_PSSR_100MBS              0x4000
#define ALASKA_PSSR_1000MBS             0x8000


#define LEVEL_ONE_LXT1000B_ID           0x207b
#define LEVEL_ONE_LXT1000B              0x3



/* assuming 1:1 mapping for virtual:physical address */

#if (_BYTE_ORDER == _BIG_ENDIAN)
#   define GEI_SYS_WRITE_REG(unit, reg, value)     \
        ((*(volatile UINT32 *)(PCI_MEMIO2LOCAL(geiResources[(unit)].memBaseLow) + (reg))) = \
         (UINT32) LONGSWAP(value))

#   define GEI_SYS_READ_REG(unit, reg)             \
        (LONGSWAP( *(volatile UINT32 *)(PCI_MEMIO2LOCAL(geiResources[(unit)].memBaseLow) + (reg))) )
#else /* (_BYTE_ORDER != _BIG_ENDIAN) */
#   define GEI_SYS_WRITE_REG(unit, reg, value)     \
        ((*(volatile UINT32 *)(PCI_MEMIO2LOCAL(geiResources[(unit)].memBaseLow) + (reg))) = \
         (UINT32)(value))

#   define GEI_SYS_READ_REG(unit, reg)             \
        (*(volatile UINT32 *)(PCI_MEMIO2LOCAL(geiResources[(unit)].memBaseLow) + (reg)))
#endif /* (_BYTE_ORDER == _BIG_ENDIAN) */

/* externs */

IMPORT END_TBL_ENTRY    endDevTbl[];    /* end device table */
IMPORT void     sysUsDelay (UINT32);

/* typedefs */
#define PPC_PAGE_SIZE       0x0001000
#define ENET_BUF_ALIGN(addr)                         \
        (((UINT32)(addr)+PPC_PAGE_SIZE) & ~(PPC_PAGE_SIZE-1))

#define EEPROM_ENABLE_BITS              9
#define EEPROM_WRITE_DIS_OPCODE         ((0x4 << 6) | (0x0 << 4))
#define EEPROM_WRITE_EN_OPCODE          ((0x4 << 6) | (0x3 << 4))
#define EEPROM_WRITE_ALL_OPCODE         ((0x4 << 6) | (0x1 << 4))
#define EEPROM_ERASE_ALL_OPCODE         ((0x4 << 6) | (0x2 << 4))

typedef struct geiResource        /* GEI_RESOURCE */
    {
    UINT32 memBaseLow;            /* Base Address LOW */
    UINT32 memBaseHigh;           /* Base Address HIGH */
    UINT32 flashBase;             /* Base Address for FLASH */
    char   irq;                   /* Interrupt Request Level */
    BOOL   adr64;                 /* Indicator for 64-bit support */
    int    boardType;             /* type of LAN board this unit is */
    int    pciBus;                /* PCI Bus number */
    int    pciDevice;             /* PCI Device number */
    int    pciFunc;               /* PCI Function number */
    UINT   memLength;             /* required memory size */
    UINT   initialStateMask;      /* mask parameter to vmStateSet */
    UINT   initialState;          /* state parameter to vmStateSet */
    UINT16 eeprom_icw1;           /* EEPROM initialization control word 1 */
    UINT16 eeprom_icw2;           /* EEPROM initialization control word 2 */
    UCHAR  enetAddr[6];           /* MAC address for this adaptor */
    STATUS iniStatus;             /* initialization perform status */
    UINT32 shMemBase;             /* Share memory address if any */
    UINT32 shMemSize;             /* Share memory size if any */
    UINT32 rxDesNum;              /* RX descriptor for this unit */
    UINT32 txDesNum;              /* TX descriptor for this unit */
    UINT32 usrFlags;              /* user flags for this unit */
    } GEI_RESOURCE;

/* locals */

LOCAL UINT32 sys543LocalToPciBusAdrs (int unit, UINT32 adrs);
LOCAL UINT32 sys543PciBusToLocalAdrs (int unit, UINT32 adrs);
LOCAL UINT32 geiUnits;     /* number of GEIs we found */

UCHAR lowMemBufGei[0xa0000 + PPC_PAGE_SIZE];


#   define VM_STATE_MASK_FOR_ALL \
           VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE |VM_STATE_MASK_CACHEABLE
#   define VM_STATE_FOR_IO \
           VM_STATE_VALID | VM_STATE_WRITABLE | VM_STATE_CACHEABLE_NOT
#   define VM_STATE_FOR_MEM_OS \
           VM_STATE_VALID | VM_STATE_WRITABLE | VM_STATE_CACHEABLE
#   define VM_STATE_FOR_MEM_APPLICATION \
           VM_STATE_VALID | VM_STATE_WRITABLE | VM_STATE_CACHEABLE
#   define VM_STATE_FOR_PCI \
           VM_STATE_VALID | VM_STATE_WRITABLE | VM_STATE_CACHEABLE_NOT


LOCAL GEI_RESOURCE geiResources [] =
    {
    {GEI0_MEMBASE0_LOW,GEI0_MEMBASE0_HIGH, GEI0_MEMBASE1, GEI0_INT_LVL,
     UNKNOWN, UNKNOWN, UNKNOWN, UNKNOWN, UNKNOWN,
     GEI0_MEMSIZE0, GEI0_INIT_STATE_MASK, GEI0_INIT_STATE, 0, 0,
     {(UCHAR)UNKNOWN}, ERROR, (UINT32)GEI0_SHMEM_BASE, GEI0_SHMEM_SIZE,
     GEI0_RXDES_NUM, GEI0_TXDES_NUM, GEI0_USR_FLAG}
     };

/* globals */

/*
 * NOTE: Each GEI device will need it's own lowMemBuf.
 * Since the PrPMC-G only has one GEI, this is all that is needed for now.
 */
                                              /* i82543 buffer in low memory */


/* forward declarations */

LOCAL int       sys543IntEnable  (int unit);
LOCAL int       sys543IntDisable (int unit);
LOCAL int       sys543IntAck     (int unit);
LOCAL void      sys543LoadStrCompose (int unit);
LOCAL STATUS    sys543eepromCheckSum (int unit);
LOCAL UINT16    sys543eepromReadWord (int unit,UINT32);
LOCAL STATUS    sys543EtherAdrGet (int unit);
LOCAL void      sys543PhySpecRegsInit(PHY_INFO *, UINT8);
LOCAL void      sys1000NsDelay (void);

LOCAL UINT32    localDramSize;

/*****************************************************************************
*
* sys543PciInit - Initialize and get the PCI configuration for 82543 Chips
*
* This routine finds out PCI device, and maps its memory and IO address.
* It must be done prior to initializing of 82543 chips.  Also
* must be done prior to MMU initialization, usrMmuInit().
*
* RETURNS: N/A
*/

STATUS sys543PciInit (void)
    {
    GEI_RESOURCE *pReso;         /* chip resources */
    int pciBus;                  /* PCI bus number */
    int pciDevice;               /* PCI device number */
    int pciFunc;                 /* PCI function number */
    int unit;                    /* unit number */

    UINT32 bar0;                 /* PCI BAR_0 */
    UINT32 memBaseLow;           /* mem base low */
    UINT32 memBaseHigh;          /* mem base High */
    UINT32 flashBase;            /* flash base */
    UINT16 boardId =0;           /* adaptor Id */
    char   irq;                  /* irq number */

#ifdef INCLUDE_PCI_AUTOCONF
    int ix;                      /* index */
    int pro1000TDevUnit=0;       /* count of Intel Pro1000T */
    int pro1000DevUnit =0;       /* count of Intel Pro1000F/T */
    BOOL duplicate;              /* BOOL flag for duplicate chip */
#endif /* INCLUDE_PCI_AUTOCONF */

    localDramSize = LOCAL_MEM_SIZE ;

    geiResources [0].shMemBase = ENET_BUF_ALIGN (lowMemBufGei);
    geiResources [0].shMemSize = sizeof(lowMemBufGei) -
                                 (ENET_BUF_ALIGN (lowMemBufGei)
     				  - (UINT32)(lowMemBufGei));

    for (unit = 0; unit < NELEMENTS(geiResources); unit++)
        {

#ifdef INCLUDE_PCI_AUTOCONF
        boardId = (UINT16)UNKNOWN;

        if (pciFindDevice (PRO1000_PCI_VENDOR_ID, PRO1000T_PCI_DEVICE_ID,
                           pro1000TDevUnit, &pciBus, &pciDevice, &pciFunc)
                           == OK)
            {
            pro1000TDevUnit++;

            boardId = PRO1000T_BOARD;
            }

        /* Detect possible PRO1000T/F adaptors */

        else if (pciFindDevice (PRO1000_PCI_VENDOR_ID, PRO1000_PCI_DEVICE_ID,
                                pro1000DevUnit, &pciBus, &pciDevice,
                                &pciFunc) == OK)
            {
            pro1000DevUnit++;

            /* Distinguish Pro1000T and Pro1000F adapter by SUB_SYSTEM_ID */

            pciConfigInWord(pciBus, pciDevice, pciFunc,
                            PCI_CFG_SUB_SYSTEM_ID, &boardId);

	    /* PrPMC-G board uses PRO1000 T */

            boardId = PRO1000T_BOARD;
            }
        else
            break;

        /* check the duplicate */

        pReso     = &geiResources [0];
        duplicate = FALSE;

        for (ix = 0; ix < NELEMENTS(geiResources); ix++, pReso++)
            {
            if ((ix != unit) && (pReso->pciBus == pciBus) &&
                (pReso->pciDevice == pciDevice) && (pReso->pciFunc == pciFunc))
                duplicate = TRUE;
            }

        if (duplicate)
            continue;

#else /* INCLUDE_PCI_AUTOCONF */

        /* manually define adaptor */
        pciBus = 0 ;
        pciDevice = 0x11 ; /* PMC #1 */
        pciFunc = 0 ;
        boardId = PRO1000_544_BOARD ;

#endif /* INCLUDE_PCI_AUTOCONF */

        /* we found the right one */

        pReso = &geiResources [unit];
        pReso->boardType = boardId;
        pReso->pciBus    = pciBus;
        pReso->pciDevice = pciDevice;
        pReso->pciFunc   = pciFunc;


        /*
         * BAR0: [32:17]: memory base
         *       [16:4] : read as "0";
         *       [3]    : 0 - device is not prefetchable
         *       [2:1]  : 00b - 32-bit address space, or
         *                01b - 64-bit address space
         *       [0]    : 0 - memory map decoded
         *
         * BAR1: if BAR0[2:1] == 00b, optional flash memory base
         *       if BAR0[2:1] == 01b, high portion of memory base
         *                            for 64-bit address space
         *
         * BAR2: if BAR0[2:1] == 01b, optional flash memory base
         *       if BAR0[2:1] == 00b, behaves as BAR-1 when BAR-0 is
         *                            a 32-bit value
         */

        pciConfigInLong (pReso->pciBus, pReso->pciDevice, pReso->pciFunc,
                          PCI_CFG_BASE_ADDRESS_0, &bar0);

        pReso->adr64 = ((bar0 & BAR0_64_BIT) == BAR0_64_BIT)? TRUE : FALSE;

        /* Set the PCI Configuration manually, if needed */

#ifndef INCLUDE_PCI_AUTOCONF

        pciConfigOutLong (pReso->pciBus, pReso->pciDevice, pReso->pciFunc,
                            PCI_CFG_BASE_ADDRESS_0, pReso->memBaseLow);
        if (pReso->adr64)
            {
            pciConfigOutLong (pReso->pciBus, pReso->pciDevice,
                                pReso->pciFunc,PCI_CFG_BASE_ADDRESS_1,
                                pReso->memBaseHigh);

            pciConfigOutLong (pReso->pciBus, pReso->pciDevice,
                                pReso->pciFunc, PCI_CFG_BASE_ADDRESS_2,
                                pReso->flashBase);
            }
        else
            {
            pciConfigOutLong (pReso->pciBus, pReso->pciDevice,
                                pReso->pciFunc, PCI_CFG_BASE_ADDRESS_1,
                                pReso->flashBase);

            pciConfigOutLong (pReso->pciBus, pReso->pciDevice,
                                pReso->pciFunc, PCI_CFG_BASE_ADDRESS_2,
                                pReso->flashBase);
            }

        pciConfigOutByte (pReso->pciBus, pReso->pciDevice, pReso->pciFunc,
                            PCI_CFG_DEV_INT_LINE, pReso->irq);

#endif /* !INCLUDE_PCI_AUTOCONF */

        /* read back memory base address and IO base address */

        pciConfigInLong (pReso->pciBus, pReso->pciDevice, pReso->pciFunc,
                          PCI_CFG_BASE_ADDRESS_0, &memBaseLow);
        if (pReso->adr64)
            {
            pciConfigInLong (pReso->pciBus, pReso->pciDevice, pReso->pciFunc,
                              PCI_CFG_BASE_ADDRESS_1, &memBaseHigh);
            pciConfigInLong (pReso->pciBus, pReso->pciDevice, pReso->pciFunc,
                              PCI_CFG_BASE_ADDRESS_2, &flashBase);
            }
        else
            {