config.h

vxworks 834x的BSP

/* wrSbc834x/config.h - Wind River SBC834x board configuration header */

/*
 * Copyright (c) 2005 Wind River Systems, Inc.
 *
 * The right to copy, distribute, modify or otherwise make use
 * of this software may be licensed only pursuant to the terms
 * of an applicable Wind River license agreement.
 */

/*
modification history
--------------------
01e,12aug05,pcm  removed INCLUDE_DOSFS from INCLUDE_TFFS auto-include list
01d,21jul05,j_b  add PCI support for gei (manual configuration)
01c,11jul05,j_b  increase LOCAL_MEM_SIZE2 for 128MB of local bus SDRAM
01b,21jun05,j_b  add NV RAM and MAC address mgmt support
01a,06jun05,kds  adapted from ads834x (rev 01e)
*/

/*
This file contains the configuration parameters for the
Wind River SBC8349 board.
*/

#ifndef INCconfigh
#define INCconfigh

#ifdef __cplusplus
extern "C" {
#endif /* __cplusplus */


/* BSP version/revision identification, should be placed
 * before #include "configAll.h"
 */

#define BSP_VER_1_1     1
#define BSP_VER_1_2     1
#define BSP_VERSION     "2.0"
#define BSP_REV         "/3"
#define BSP_NAME        wrSbc834x

#include "configAll.h"

/* Define Clock Speed and source  */

#define FREQ_33_MHZ      33000000
#define FREQ_40_MHZ      40000000
#define FREQ_66_MHZ      66000000
#define FREQ_100_MHZ     100000000
#define FREQ_266_MHZ     266000000
#define FREQ_333_MHZ     333000000

/*
 * This define must be set to the value of the resonant oscillator
 * inserted in position U16 or the PCI freq of the wrSbc834x board.
 * Choose from above list.
 */
#define OSCILLATOR_FREQ FREQ_66_MHZ

/*
 * These default values assume CSB is 266Mhz based on HRCW setting in
 *  boot image
 */
#define SYS_CLK_FREQ            FREQ_266_MHZ
#define DEC_CLK_TO_INC          4               /* # bus clks per increment */
#define DEC_CLOCK_FREQ          SYS_CLK_FREQ    /* Set to system default */
#define TIMESTAMP_HZ            SYS_CLK_FREQ

#define TPR         0x2000
#define LSRT_VALUE  0x20

/* Memory addresses */

#define LOCAL_MEM_SIZE          0x10000000      /* 256 Mbytes available */
#define LOCAL_MEM_LOCAL_ADRS    0x00000000      /* Base of RAM */
#define INCLUDE_LBC_SDRAM
#define INCLUDE_DDR_SDRAM
#define INCLUDE_SECONDARY_DRAM
/* NOTE this should match the LAWAR SIZE in romInit for the chosen SDRAM */
#define LOCAL_MEM_SIZE2             0x8000000       /* 128 Mbytes available */
#define LOCAL_MEM_LOCAL_ADRS2       0x10000000      /* Base of RAM */
#define LBC_SDRAM_LOCAL_SIZE_MASK   0xfc000000
#define LBC_SDRAM_LOCAL_ADRS        LOCAL_MEM_LOCAL_ADRS2
#define LBC_SDRAM_LOCAL_SIZE        LOCAL_MEM_SIZE2
#define DDR_SDRAM_LOCAL_ADRS        LOCAL_MEM_LOCAL_ADRS
#define DDR_SDRAM_LOCAL_SIZE        LOCAL_MEM_SIZE
#define DDR_SDRAM_LOCAL_ADRS_END   (DDR_SDRAM_LOCAL_ADRS + DDR_SDRAM_LOCAL_SIZE)

/*
 * The constants ROM_TEXT_ADRS, ROM_SIZE, and RAM_HIGH_ADRS are defined
 * in config.h, MakeSkel, Makefile, and Makefile.*
 * All definitions for these constants must be identical.
 */

#define ROM_BASE_ADRS   0xff800000      /* base address of ROM */
#define ROM_TEXT_ADRS   0xfff00100
#define ROM_SIZE        0x100000         /* ROM space */
#define ROM_WARM_ADRS   (ROM_TEXT_ADRS+8) /* warm reboot entry */


/* RAM address for ROM boot */
#define RAM_HIGH_ADRS   0x00e00000

/* RAM address for sys image */
#define RAM_LOW_ADRS    0x00010000

#define USER_RESERVED_MEM    0x00000000 /* user reserved memory size */

#define DEFAULT_BOOT_LINE \
"mottsec(0,0)host:target/config/wrSbc834x/vxWorks h=92.0.0.1 e=92.0.0.2 u=vxworks pw=vxworks tn=wrSbc834x"

#define INCLUDE_MMU_BASIC

#ifdef  INCLUDE_MMU_BASIC
#   define USER_I_MMU_ENABLE
#   define USER_D_MMU_ENABLE
#endif

#define INCLUDE_CACHE_SUPPORT

#ifdef  INCLUDE_CACHE_SUPPORT
#   define USER_D_CACHE_ENABLE
/* Does nothing about copyback vs writethrough in h/w, must use sysPhysMemDesc */
#   undef  USER_D_CACHE_MODE
#   define USER_D_CACHE_MODE  CACHE_COPYBACK | CACHE_SNOOP_ENABLE
#   define USER_I_CACHE_ENABLE
#   undef  USER_I_CACHE_MODE
#   define USER_I_CACHE_MODE  CACHE_COPYBACK
#endif

/* Number of TTY definition */

#undef  NUM_TTY
#define NUM_TTY     N_SIO_CHANNELS  /* defined in wrSbc834x.h */

#undef   CONSOLE_TTY
#define CONSOLE_TTY    0  /* 0 = UART1/COM1, 1 = UART2/COM2 */


/* Optional timestamp support */

#undef INCLUDE_TIMESTAMP
#define INCLUDE_AUX_CLK

#undef INCLUDE_DMA

/* optional TrueFFS support */

#undef  INCLUDE_TFFS

#ifdef INCLUDE_TFFS
#endif  /* INCLUDE_TFFS */


/* clock rates */

#define SYS_CLK_RATE_MIN    1   /* minimum system clock rate */
#define SYS_CLK_RATE_MAX    8000    /* maximum system clock rate */
#define AUX_CLK_RATE_MIN    1   /* minimum auxiliary clock rate */
#define AUX_CLK_RATE_MAX    8000    /* maximum auxiliary clock rate */


/* add on-chip drivers */
#undef INCLUDE_SECURITY_ENGINE /* only support if chip has E ie 8349E */

#undef INCLUDE_PIB_SUPPORT      /* include PIB IO board support */
#undef INCLUDE_PCI      /* include PCI library support */

#ifdef  INCLUDE_PCI
#  undef INCLUDE_PCI_AUTOCONF

/*
CPU Addr                    PCI Addr
PCI_LOCAL_MEM_BUS   ------------------------- PCI_MSTR_MEM_BUS
            -               -
                -               -
PCI_LOCAL_MEM_BUS + ------------------------- PCI_MSTR_MEM_BUS +
PCI_LOCAL_MEM_SIZE  ----IMMR                - PCI_MSTR_MEM_SIZE
                -               -
                -               -----PIMMR
                -               -
                -               -
CPU_PCI_MEM_ADRS    ------------------------- PCI_MEM_ADRS
                    -           -
                -           -
CPU_PCI_MEMIO_ADRS  ------------------------- PCI_MEMIO_ADRS
                    -           -
                -               -
CPU_PCI_IO_ADRS     ------------------------- PCI_IO_ADRS
                -               -
                -               -
CPU_PCI_IO_ADRS +   ------------------------- PCI_IO_ADRS +
CPU_PCI_IO_SIZE     -               - PCI_IO_SIZE
                -               -
                -               -
                -               -
                -------------------------- 4GBytes
*/



/* for custom sysPciAutoConfig.c */


/* PCI based addresses */
#  define PCI_MEM_ADRS        0x80000000
#  define PCI_MEM_SIZE        0x10000000      /* 256MB */
#  define PCI_MEM_SIZE_MASK   PCI_SIZE_256MB  /* Mask to match PCI_MEM_SIZE */
#  define PCI_MEMIO_ADRS      0x90000000
#  define PCI_MEMIO_SIZE      0x10000000      /* 256MB */
#  define PCI_MEMIO_SIZE_MASK PCI_SIZE_256MB  /* Mask to match PCI_MEMIO_SIZE */
#  define PCI_IO_ADRS         0xa0000000
#  define PCI_IO_SIZE         0x10000000      /* 256MB */


/* CPU based addresses */
#  define CPU_PCI_MEM_ADRS        0x80000000
#  define CPU_PCI_MEM_SIZE        PCI_MEM_SIZE
#  define CPU_PCI_MEMIO_ADRS      0x90000000
#  define CPU_PCI_MEMIO_SIZE      PCI_MEMIO_SIZE
#  define CPU_PCI_IO_ADRS         0xa0000000
#  define CPU_PCI_IO_SIZE         PCI_IO_SIZE


/* CPU from PCI bus */
#  define PCI_MSTR_MEM_BUS        0x00000000
#  define PCI_MSTR_MEM_SIZE       PCI_LOCAL_MEM_SIZE
#  define PCI_BRIDGE_PIMMR_BASE_ADRS      0x40000000


/* CPU Address that is visible from PCI */
#  define PCI_LOCAL_MEM_BUS   LOCAL_MEM_LOCAL_ADRS
#  define PCI_LOCAL_MEM_SIZE  LOCAL_MEM_SIZE
/* This should at least match size of LOCAL_MEM_SIZE */
#  define PCI_LOCAL_MEM_SIZE_MASK PCI_SIZE_256MB

#endif /* INCLUDE_PCI */


/* add necessary drivers */

#define INCLUDE_MOT_TSEC_END

#ifdef INCLUDE_MOT_TSEC_END
#  ifndef INCLUDE_END
#    define INCLUDE_END  /* only END-style driver for FCC */
#  endif /* INCLUDE_END */
#endif /* INCLUDE_MOT_TSEC_END */

#ifdef INCLUDE_MOT_TSEC_END
#define INCLUDE_PRIMARY_TSEC_END      /* primary */
#define INCLUDE_SECONDARY_TSEC_END    /* secondary */
#endif /* INCLUDE_MOT_TSEC_END */


#ifdef INCLUDE_PCI
#  define INCLUDE_GEI_END
#endif

#define INCLUDE_FLASH


#ifdef INCLUDE_FLASH
#  define SYS_FLASH_TYPE        FLASH_28F640J3A    /* flash device type */
#  define FLASH_WIDTH           2
#  define FLASH_CHIP_WIDTH      1
#  define FLASH_SEGMENT_SIZE    0x10000
#  define FLASH_ADRS            0xfffe0000
#  define FLASH_SIZE            FLASH_SEGMENT_SIZE
#  define FLASH_SIZE_WRITEABLE  FLASH_SEGMENT_SIZE
#  define FLASH_WIDTH_SPECIAL_2
#  undef FLASH_NO_OVERLAY
#endif

#define FLASH_BASE_ADRS     0xff800000
#define FLASH_WINDOW_SIZE   0x00400000

/* MAC Address configuration */

#define MAC_ADRS_LEN    6   /* 6 bytes in MAC address */
#define MAX_MAC_ADRS    2   /* number of MAC addresses to save in EEPROM */

#define ETHERNET_MAC_HANDLER   /* enable 'M' command */

/*
 * The Ethernet hardware address is of the form
 *
 *       00:A0:1E:nn:nn:nn
 *
 * where the first three bytes are defined below, and last three bytes are
 * user specified.
 */

#define WR_ENET0        0x00  /* WR specific portion of MAC (MSB->LSB) */
#define WR_ENET1        0xA0
#define WR_ENET2        0x1E

#define CUST_ENET3      0x11  /* Customer portion of MAC address */
#define CUST_ENET4      0x12
#define CUST_ENET5_0    0x00
#define CUST_ENET5_1    0x00

#define ENET_DEFAULT    0x1EA00000 /* WR fixed MAC addr; see WR_ENETx */

/* Non-volatile memory configuration */

#define NV_RAM_SIZE          EEPROM_SIZE /* 8K bytes non-volatile memory */
#define NV_RAM_ADRS          EEPROM_BASE_ADRS
#define NV_RAM_INTRVL        1

#if (NV_RAM_SIZE != NONE)
#  define SMART_EEPROM_WRITE     /* skip EEPROM write if value isn't changing */
#  define INCLUDE_EEPROM_LOCKING /* lock eeprom via software protection    */

#  undef  NV_BOOT_OFFSET       /* room for MAC addresses  */

  /* Define offsets for non-volatile data  */

#  define NV_BOOT_OFFSET       0  /* boot line parameters */
#  define NV_MAC_ADRS_OFFSET   (BOOT_LINE_SIZE + 1)  /* MAC addresses */
/* next available area */
#  define NV_USER_OFFSET    (NV_MAC_ADRS_OFFSET + (MAC_ADRS_LEN * MAX_MAC_ADRS))
#endif  /* NV_RAM_SIZE != NONE */

/* Hard Reset Configuration Words */

/* See MPC8349E hardware specification for supported clock freq */
/* spmf 1:5 ie 4*66Mhz == 266Mhz CSB*/
#define HRCW_LOW_BYTE0  0x04
/* corepll ratio 400Mhz  */
#define HRCW_LOW_BYTE1  0x23
/* Must be cleared*/
#define HRCW_LOW_BYTE2  0x00
/* Must be cleared*/
#define HRCW_LOW_BYTE3  0x00


/* Pci host,2* 32 bit buses,arbiters disabled */
#define HRCW_HIGH_BYTE0  HRCW_HIGH_PCI_HOST | HRCW_HIGH_PCI1_ARB | HRCW_HIGH_PCI64
/* Rom Location Flash 16 bit. Watch dog disabled  */
#define HRCW_HIGH_BYTE1  ROMLOC_GPCM_16BIT
/* GMII */
#define HRCW_HIGH_BYTE2  HRCW_HIGH_TSEC12M_GMII /* Both TSECs use GMII */
/* Big Endian */
#define HRCW_HIGH_BYTE3  0x00

/*
 * Default power management mode - selected via vxPowerModeSet() in
 * sysHwInit().
 */

#define DEFAULT_POWER_MGT_MODE  VX_POWER_MODE_DISABLE

#define INCLUDE_SYSLED

#undef  INCLUDE_BSP_VTS           /* For BSP validation */
#ifdef  INCLUDE_BSP_VTS

#define INCLUDE_SHELL
#define INCLUDE_LOADER
#define INCLUDE_UNLOADER
#define INCLUDE_SYM_TBL
#define INCLUDE_NET_SHOW
#define INCLUDE_RLOGIN
#define INCLUDE_TELNET
#define INCLUDE_NET_SYM_TBL
#define INCLUDE_PING
#define INCLUDE_SHOW_ROUTINES
#define INCLUDE_DISK_UTIL
#define INCLUDE_ICMP_SHOW
#define INCLUDE_TCP_SHOW
#define INCLUDE_UDP_SHOW
#define INCLUDE_IGMP_SHOW
#define INCLUDE_NET_IF_SHOW     /* Interface show routines */
#define INCLUDE_NET_SHOW
#define INCLUDE_DISK_UTIL
#define INCLUDE_IFCONFIG
#define INCLUDE_IFLIB
#define INCLUDE_ROUTECMD        /* routec command-line utility */

#endif /* INCLUDE_BSP_VTS */

#include "wrSbc834x.h"          /* include the wrSbc834x params */

#ifdef __cplusplus
}
#endif /* __cplusplus */

#endif  /* INCconfigh */
#if defined(PRJ_BUILD)
    #include "prjParams.h"
#endif