wrsbc834x.h

vxworks 834x的BSP

#define  PCI_SIZE_4KB     0x0000000B
#define  PCI_SIZE_8KB     0x0000000C
#define  PCI_SIZE_16KB    0x0000000D
#define  PCI_SIZE_32KB    0x0000000E
#define  PCI_SIZE_64KB    0x0000000F
#define  PCI_SIZE_128KB   0x00000010
#define  PCI_SIZE_256KB   0x00000011
#define  PCI_SIZE_512KB   0x00000012
#define  PCI_SIZE_1MB     0x00000013
#define  PCI_SIZE_2MB     0x00000014
#define  PCI_SIZE_4MB     0x00000015
#define  PCI_SIZE_8MB     0x00000016
#define  PCI_SIZE_16MB    0x00000017
#define  PCI_SIZE_32MB    0x00000018
#define  PCI_SIZE_64MB    0x00000019
#define  PCI_SIZE_128MB   0x0000001A
#define  PCI_SIZE_256MB   0x0000001B
#define  PCI_SIZE_512MB   0x0000001C
#define  PCI_SIZE_1GB     0x0000001D
#define  PCI_SIZE_2GB     0x0000001E


/* Offsets for DDR registers */
#define DDRBA      (CCSBAR | DDR_REG_BA)
#define CS0_BNDS   0x000
#define CS1_BNDS   0x008
#define CS2_BNDS   0x010
#define CS3_BNDS   0x018
#define CS0_CONFIG 0x080
#define CS1_CONFIG 0x084
#define CS2_CONFIG 0x088
#define CS3_CONFIG 0x08C

#define TIMING_CFG_1 0x108
#define TIMING_CFG_2 0x10C
#define DDR_SDRAM_CFG 0x110
#define DDR_SDRAM_MODE_CFG 0x118
#define DDR_SDRAM_INTERVAL 0x124
#define DDR_SDRAM_CLK_CNTRL 0x130

#define DDR_DATA_ERR_INJECT_HI 0xe00
#define DDR_DATA_ERR_INJECT_LO 0xe04
#define DDR_ECC_ERR_INJECT 0xe08
#define DDR_CAPTURE_DATA_HI 0xe20
#define DDR_CAPTURE_DATA_LO 0xe24
#define DDR_CAPTURE_ECC 0xe28
#define DDR_ERR_DETECT 0xe40
#define DDR_ERR_DISABLE 0xe44
#define DDR_ERR_INT_EN 0xe48
#define DDR_CAPTURE_ATTRIBUTES 0xe4c
#define DDR_CAPTURE_ADDRESS 0xe50
#define DDR_ERR_SBE 0xe58

/* add PCI access macros */
#define PCI_MEMIO2LOCAL(x) \
         (((UINT32)x  - PCI_MEMIO_ADRS) + CPU_PCI_MEMIO_ADRS)
/* PCI IO memory adrs to CPU (60x bus) adrs */

#define PCI_IO2LOCAL(x) \
     (((UINT32)x  - PCI_IO_ADRS) + CPU_PCI_IO_ADRS)

#define PCI_MEM2LOCAL(x) \
         (((UINT32)x  - PCI_MEM_ADRS) + CPU_PCI_MEM_ADRS)

/* 60x bus adrs to PCI (non-prefetchable) memory address */

#define LOCAL2PCI_MEMIO(x) \
     ((int)(x) + PCI_MSTR_MEM_BUS)


/* PCI defines begin */


/* configuration space reg and int ack */

#define PCI_CFG_ADR_REG        (CCSBAR + PCICFG_REG_BA + 0x00)
#define PCI_CFG_DATA_REG       (CCSBAR + PCICFG_REG_BA + 0x04)
#define PCI_INT_ACK            (CCSBAR + PCICFG_REG_BA + 0x08)

#define PCI_AUTO_CONFIG_ADRS  0x4c00

#define PPCACR_PRKM_MASK 0XF0
#define PCI_REQUEST_LEVEL 0x3

#define CLASS_OFFSET      0xB
#define CLASS_WIDTH       0x1
#define BRIDGE_CLASS_TYPE 0x6


#define PCICMD_ADRS     (PCI_CFG_BASE + 0x04)  /* PCI cmd reg */
#define PCICMD_VAL      0x00000006             /* PCI COMMAND Default value */
#define PCISTAT_ADRS    (PCI_CFG_BASE + 0x06)  /* PCI status reg */

#define NUM_PCI_SLOTS           0x1            /* One PCI slot */

#define PCI_XINT1_LVL           0x0            /* PCI XINT1 routed to IRQ0  */
#define PCI_XINT2_LVL           0x1            /* PCI XINT2 routed to IRQ1 */
#define PCI_XINT3_LVL           0x2            /* PCI XINT3 routed to IRQ2 */
#define PCI_XINT4_LVL           0x3            /* PCI XINT3 routed to IRQ2 */

#define PCI_SLOT1_DEVNO        0x11            /* PCI SLOT Device no */

#define PCI_LAT_TIMER          0x40            /* latency timer value, 64 PCI clocks */

#define PCI1_DEV_ID      0x826010E3
#define PCI2_DEV_ID      0x826110E3
#define PCI3_DEV_ID      0x826210E3
#define PCI_DEV_ID_82XX  0x00031057  /* Id for MPC8266ADS-PCI board - Rev1 */
#define PCI_DEV_ID_85XX  0x00091057  /* Id for MPC85xxADS-PCI board - Rev2 */
#define PCI_ID_I82559           0x12298086     /* Id for Intel 82559 */
#define PCI_ID_I82559ER         0x12098086     /* Id for Intel 82559 ER */

#define MPC8266ADS_PCI_IRQ       INUM_PCI1

#define PCI_INTA_IRQ     MPC8266ADS_PCI_IRQ
#define PCI_INTB_IRQ     MPC8266ADS_PCI_IRQ
#define PCI_INTC_IRQ     MPC8266ADS_PCI_IRQ
#define PCI_INTD_IRQ     MPC8266ADS_PCI_IRQ

#define DELTA(a,b)      (sysAbs((int)a - (int)b))

#define BUS 0               /* bus-less board */

/* Board Status and Control Registers - unique to ADS */
         /* Chip Select 1 for 8349E board */

#define EEPROM_BASE_ADRS    0xF8000000      /* EEPROM base address */
#define EEPROM_SIZE      0x00002000         /* 8K of address space */
#define EEPROM_MASK      ~(EEPROM_SIZE - 1) /* 8K mask for EEPROM */


/* CPU type in the PVR */

#define CPU_TYPE_8260           0xAAAA      /* value for PPC8260 */
#define CPU_TYPE_8266           0xBBBB      /* value for PPC8266 */
#define CPU_REV_A1_MASK_NUM     0x0010      /* revision mask num */
#define HIP4_ID                 0x80810000  /* device ID via PVR */
#define HIP4_MASK               0xFFFF0000  /* mask upper word   */
#define HIP7_ID             0x80820000

    /* Default Values */
#define SPCR_DEFAULT_VAL                0x13020000
#define SICRL_DEFAULT_VAL               0x80000000
#define SICRH_DEFAULT_VAL               0x00000003
#define OCCR_DEFAULT_VAL                0x80000000
#define ATR_DEFAULT_VAL                 0x00ff00ff
#define AIDR_DEFAULT_VAL                0x0000003f
#define AERR_DEFAULT_VAL                0x00000000
#define AMR_DEFAULT_VAL                 0x00000007
#define ACR_DEFAULT_VAL                 0x00100000
#define AER_DEFAULT_VAL                 0x0000003f

/* romInit initialization values... */

/* Values for local bus windows before flash is remapped at powerup. */

#define LBLAWBAR0_BOOT_VAL              0x00000000
/* 2 GB */
#define LBLAWAR0_BOOT_VAL               (LAWAR_ENABLE|LAWAR_SZ_2GB)

#define LBLAWBAR1_BOOT_VAL              0x80000000
/* 2 GB */
#define LBLAWAR1_BOOT_VAL               (LAWAR_ENABLE|LAWAR_SZ_2GB)

#define LBLAWBAR2_BOOT_VAL              0x00000000
#define LBLAWAR2_BOOT_VAL               0x00000000

#define LBLAWBAR3_BOOT_VAL              0x00000000
#define LBLAWAR3_BOOT_VAL               0x00000000

#define BR0_DEFAULT_VAL                 (ROM_BASE_ADRS|0x1001)
/*
For SRAM:
#define OR0_DEFAULT_VAL                 0xff806fa0
*/
/* I also think this needs to be fixed for flash for machine check to work -
   will check on a flash ready board. */
#define OR0_DEFAULT_VAL                 0xff806ff7

#define LBLAWBAR0_DEFAULT_VAL           ROM_BASE_ADRS
/* 8MB */
#define LBLAWAR0_DEFAULT_VAL            (LAWAR_ENABLE|LAWAR_SZ_8MB)

#define LBLAWBAR1_DEFAULT_VAL           EEPROM_BASE_ADRS
#define LBLAWAR1_DEFAULT_VAL            (LAWAR_ENABLE|LAWAR_SZ_8KB)

#define PCILAWBAR0_DEFAULT_VAL          0x80000000
/* 256 MB */
#define PCILAWAR0_DEFAULT_VAL           0x8000001b

#define PCILAWBAR1_DEFAULT_VAL          0x90000000
/* 256 MB */
#define PCILAWAR1_DEFAULT_VAL           0x8000001b

#define BR1_DEFAULT_VAL                 (EEPROM_BASE_ADRS|0x801)
#define OR1_DEFAULT_VAL                 0xffff60f6


/* Hard Reset Configuration Words */
/* Low Word */
/*Byte 0*/
#define HRCW_LOW_LBIU_DIV2   0x80
#define HRCW_LOW_DDR_DIV2    0x40
#define HRCW_LOW_SPMF        0x0f

/* Byte 1*/
#define HRCW_LOW_CORE_PLL   0xFF

/* byte 2 and 3 must be cleared */

/* High Word */
/*Byte 0*/
#define HRCW_HIGH_PCI_HOST     0x80
#define HRCW_HIGH_PCI64        0x40
#define HRCW_HIGH_PCI1_ARB     0x20
#define HRCW_HIGH_PCI2_ARB     0x10
#define HRCW_HIGH_CORE_DIS     0x08
#define HRCW_HIGH_BMS_HIGH     0x04
#define HRCW_HIGH_BOOT_SEQ_I2C 0x01
#define HRCW_HIGH_BOOT_SEQ_EXT_I2C 0x02

/*Byte 1*/
#define HRCW_HIGH_SWEN         0x80
#define HRCW_HIGH_ROMLOC       0x70
#define ROMLOC_DDR        0x00
#define ROMLOC_PCI1       0x10
#define ROMLOC_PCI2       0x20
#define ROMLOC_GPCM_8BIT  0x50
#define ROMLOC_GPCM_16BIT 0x60
#define ROMLOC_GPCM_32BIT 0x70


/*Byte 2*/
#define HRCW_HIGH_TSEC1M       0xc0
#define HRCW_HIGH_TSEC2M       0x30

#define HRCW_HIGH_TSEC12M_GMII 0xa0

/*Byte 3*/
#define HRCW_HIGH_TLE          0x40


#ifndef _ASMLANGUAGE

/* function declarations */
extern uint32_t sysBaudClkFreq(void);
extern void   sysMsDelay(uint32_t);
extern void   sysDelay(void);
extern uint32_t sysAbs(int);
extern uint32_t sysDecGet(void);
extern UINT32 vxHid2Get();
extern void   vxHid2Set(UINT32);
extern UINT32 vxSvrGet();
#endif /* _ASMLANGUAGE */

#ifdef __cplusplus
}
#endif /* __cplusplus */

#endif /* INCwrSbc834xh */