wrsbc834x.h

vxworks 834x的BSP

/* wrSbc834x.h - Wind River SBC834x board header */

/*
 * Copyright (c) 2005 Wind River Systems, Inc.
 *
 * The right to copy, distribute, modify or otherwise make use
 * of this software may be licensed only pursuant to the terms
 * of an applicable Wind River license agreement.
 */

/*
modification history
--------------------
01a,22jun05,j_b  adapted from ads834x (rev 01a); remove extraneous NvRAM macros
*/

/*
This file contains I/O addresses and related constants for the
Wind River SBC8349 board.
*/

#ifndef INCwrSbc834xh
#define INCwrSbc834xh

#ifdef __cplusplus
extern "C" {
#endif /* __cplusplus */

#ifndef EIEIO_SYNC
#   define EIEIO_SYNC  _WRS_ASM (" eieio; sync")
#endif        /* EIEIO_SYNC */
#ifndef EIEIO
#   define EIEIO    _WRS_ASM (" eieio")
#endif        /* EIEIO */


#ifndef  _ASMLANGUAGE
# if (defined(_WRS_VXWORKS_MAJOR) && (_WRS_VXWORKS_MAJOR >= 6))
/* nothing needed */
# else  /* _WRS_VXWORKS_MAJOR */
typedef void * VIRT_ADDR;
typedef void * PHYS_ADDR;
# endif  /* _WRS_VXWORKS_MAJOR */
#endif  /* _ASMLANGUAGE */

#ifndef M8260ABBREVIATIONS
#define M8260ABBREVIATIONS

#ifdef  _ASMLANGUAGE
#define CAST(x)
#else /* _ASMLANGUAGE */
typedef volatile UCHAR VCHAR;   /* shorthand for volatile UCHAR */
typedef volatile INT32 VINT32; /* volatile unsigned word */
typedef volatile INT16 VINT16; /* volatile unsigned halfword */
typedef volatile INT8 VINT8;   /* volatile unsigned byte */
typedef volatile UINT32 VUINT32; /* volatile unsigned word */
typedef volatile UINT16 VUINT16; /* volatile unsigned halfword */
typedef volatile UINT8 VUINT8;   /* volatile unsigned byte */
#define CAST(x) (x)
#endif  /* _ASMLANGUAGE */

#endif /* M8260ABBREVIATIONS */

#undef  CPU
#define CPU PPC603              /* CPU type */

#define N_SIO_CHANNELS      2       /* No. serial I/O channels */

/* define the decrementer input clock frequency */
#define SPD_DATA_SIZE         128

/* Base Address of Memory Mapped Registers */
#define CCSBAR_INIT  0xFF400000
#define CCSBAR       0xFF400000
#define CCSBAR_SIZE  0x100000 /* 1MB */

/* Register Set Base addresses */
#define PQ2PRO

#define SCCFG_REG_BA           0x00100
#define WDT_REG_BA             0x00200
#define QUICC_RTC_BASE         0x00300
#define QUICC_PIT_BASE         0x00400
#define QUICC_GTM1_BASE        0x00500
#define QUICC_GTM2_BASE        0x00600
#define SIC_REG_BA             0x00700
#define ARBITER_REG_BA         0x00800
#define RESETM_REG_BA          0x00900

#define CLKM_REG_BA            0x00A00
#define GPIO1_REG_BA           0x00C00
#define DDR_REG_BA             0x02000
#define LBC_REG_BA             0x05000
#define DMA_REG_BA             0x08100
#define PCICFG_REG_BA          0x08300
#define SEC_REG_BA             0x101B4


#define DMA_NUM 4
/* Define the register definition and interrupt numbers based on
 * cpu varient */

#include <drv/intrCtl/quiccIntrCtl.h>
#include <drv/mem/quiccLbc.h>

/* system & processor version */


/* System Configuration Control */

#define M83XX_SGPRL(base)  (CAST(VUINT32 *)((base) + SCCFG_REG_BA + 0x00 ))
#define M83XX_SGPRH(base)  (CAST(VUINT32 *)((base) + SCCFG_REG_BA + 0x04 ))
#define M83XX_SPRIDR(base) (CAST(VUINT32 *)((base) + SCCFG_REG_BA + 0x08 ))


#define M83XX_SPCR(base)  (CAST(VUINT32 *)((base) +  SCCFG_REG_BA + 0x10 ))
#define M83XX_SPCR_OPT 0x00800000
#define M83XX_SPCR_TBEN 0x00400000

#define M83XX_SICRL(base)  (CAST(VUINT32 *)((base) + SCCFG_REG_BA + 0x14 ))
#define M83XX_SICRH(base)  (CAST(VUINT32 *)((base) + SCCFG_REG_BA + 0x18 ))



/* Watch Dog Registers */

#define M83XX_SWCRR(base)  (CAST(VUINT32 *)((base) + WDT_REG_BA + 0x04 ))
#define M83XX_SWCNR(base)  (CAST(VUINT32 *)((base) + WDT_REG_BA + 0x08 ))
#define M83XX_SWSRR(base)  (CAST(VUINT16 *)((base) + WDT_REG_BA + 0x0E ))


/* Clock Module */
#define M83XX_SPMR(base)  (CAST(VUINT32 *)((base) + CLKM_REG_BA + 0x00 ))
#define M83XX_SPMR_LBIU_VAL(spmrVal) (spmrVal >> 31);
#define M83XX_SPMR_DDR_VAL(spmrVal) (spmrVal >> 30) & 0x1;
#define M83XX_SPMR_SPMF_VAL(spmrVal) (spmrVal >> 24) & 0xf;
#define M83XX_SPMR_CLK_DIV(spmrVal) (spmrVal >> 23) & 0x1;
#define M83XX_SPMR_CLK_PLL(spmrVal) (spmrVal >> 16) & 0x7f;

#define M83XX_OCCR(base)  (CAST(VUINT32 *)((base) + CLKM_REG_BA + 0x04 ))
#define M83XX_SCCR(base)  (CAST(VUINT32 *)((base) + CLKM_REG_BA + 0x08 ))

#define M83XX_SCCR_RES_MSK      0xf3f10000      /* reserved field Mask */

/* Arbiter registers*/

#define M83XX_ACR(base)   (CAST(VUINT32 *)((base) + ARBITER_REG_BA + 0x00))
#define M83XX_ATR(base)   (CAST(VUINT32 *)((base) + ARBITER_REG_BA + 0x04))
#define M83XX_AER(base)   (CAST(VUINT32 *)((base) + ARBITER_REG_BA + 0x0c))
#define M83XX_AIDR(base)   (CAST(VUINT32 *)((base) + ARBITER_REG_BA + 0x10))
#define M83XX_AMR(base)   (CAST(VUINT32 *)((base) + ARBITER_REG_BA + 0x14))
#define M83XX_AEATR(base)   (CAST(VUINT32 *)((base) + ARBITER_REG_BA + 0x18))
#define M83XX_AEADR(base)   (CAST(VUINT32 *)((base) + ARBITER_REG_BA + 0x1c))
#define M83XX_AERR(base)   (CAST(VUINT32 *)((base) + ARBITER_REG_BA + 0x20))

/* Reset Configuration Module */

#define M83XX_RCWLR(base)   (CAST(VUINT32 *)((base) + RESETM_REG_BA + 0x00))
#define M83XX_RCWHR(base)   (CAST(VUINT32 *)((base) + RESETM_REG_BA + 0x04))
#define M83XX_RSR(base)     (CAST(VUINT32 *)((base) + RESETM_REG_BA + 0x10))
#define M83XX_RMR(base)   (CAST(VUINT32 *)((base) + RESETM_REG_BA + 0x14))
#define M83XX_RPR(base)   (CAST(VUINT32 *)((base) + RESETM_REG_BA + 0x18))
#define M83XX_RCR(base)   (CAST(VUINT32 *)((base) + RESETM_REG_BA + 0x1c))
#define M83XX_RCER(base)   (CAST(VUINT32 *)((base) + RESETM_REG_BA + 0x20))

/* GPIO Registers */

#define M83XX_GP1DIR(base)    (CAST(VUINT32 *)((base) + GPIO1_REG_BA + 0x00))
#define M83XX_GP1DAT(base)    (CAST(VUINT32 *)((base) + GPIO1_REG_BA + 0x08))

/* I2C1 Controller */

#define  M834X_I2C1_BASE                 0x03000

#define  I2C1ADR    0x03000
#define  I2C1FDR    0x03004
#define  I2C1ICR    0x03008
#define  I2C1ISR    0x0300c
#define  I2C1IDR    0x03010
#define  I2C1DFSRR  0x03014

#define  M834X_I2C1ADR(base)            (CAST(VUINT8 *)((base) | I2C1ADR))
#define  M834X_I2C1FDR(base)            (CAST(VUINT8 *)((base) | I2C1FDR))
#define  M834X_I2C1ICR(base)            (CAST(VUINT8 *)((base) | I2C1ICR))
#define  M834X_I2C1ISR(base)            (CAST(VUINT8 *)((base) | I2C1ISR))
#define  M834X_I2C1IDR(base)            (CAST(VUINT8 *)((base) | I2C1IDR))
#define  M834X_I2C1DFSRR(base)          (CAST(VUINT32 *)((base) | I2C1DFSRR))


/* I2C2 Controller */

#define  M834X_I2C2_BASE                 0x03100

#define  I2C2ADR    0x03100
#define  I2C2FDR    0x03104
#define  I2C2ICR    0x03108
#define  I2C2ISR    0x0310c
#define  I2C2IDR    0x03110
#define  I2C2DFSRR  0x03114

#define  M834X_I2C2ADR(base)            (CAST(VUINT8 *)((base) | I2C2ADR))
#define  M834X_I2C2FDR(base)            (CAST(VUINT8 *)((base) | I2C2FDR))
#define  M834X_I2C2ICR(base)            (CAST(VUINT8 *)((base) | I2C2ICR))
#define  M834X_I2C2ISR(base)            (CAST(VUINT8 *)((base) | I2C2ISR))
#define  M834X_I2C2IDR(base)            (CAST(VUINT8 *)((base) | I2C2IDR))
#define  M834X_I2C2DFSRR(base)          (CAST(VUINT32 *)((base) | I2C2DFSRR))


/* Security IMMR registers */
#define QUICC_SECBR(base) (CAST(VUINT32 *)((base) + SEC_REG_BA + 0x0))
#define QUICC_SECMR(base) (CAST(VUINT32 *)((base) + SEC_REG_BA + 0x4))

#define SEC_ENG_BASE_ADRS (CCSBAR + 0x40000)
#define SEC_ENG_SIZE      0x20000
#define SEC_ENG_SIZE_MASK 0xfffe0000

/* Local address windows */

#define M83XX_LBLAWBARn(base,n)      \
       (CAST(VUINT32 *)((base) + 0x20 + (n*0x8)))

#define M83XX_LBLAWARn(base,n)      \
       (CAST(VUINT32 *)((base) + 0x24 + (n*0x8)))

#define M83XX_PCILAWBARn(base,n)      \
       (CAST(VUINT32 *)((base) + 0x60 + (n*0x8)))

#define M83XX_PCILAWARn(base,n)      \
       (CAST(VUINT32 *)((base) + 0x64 + (n*0x8)))

#define M83XX_DDRLAWBARn(base,n)      \
       (CAST(VUINT32 *)((base) + 0xA0 + (n*0x8)))

#define M83XX_DDRLAWARn(base,n)      \
       (CAST(VUINT32 *)((base) + 0xA4 + (n*0x8)))

#define LAWBAR_ADRS_SHIFT  0

#define  LAWAR_ENABLE       0x80000000
/* LAWAR SIZE Settings */
#define  LAWAR_SIZE_4KB     0x0000000B
#define  LAWAR_SIZE_8KB     0x0000000C
#define  LAWAR_SIZE_16KB    0x0000000D
#define  LAWAR_SIZE_32KB    0x0000000E
#define  LAWAR_SIZE_64KB    0x0000000F
#define  LAWAR_SIZE_128KB   0x00000010
#define  LAWAR_SIZE_256KB   0x00000011
#define  LAWAR_SIZE_512KB   0x00000012
#define  LAWAR_SIZE_1MB     0x00000013
#define  LAWAR_SIZE_2MB     0x00000014
#define  LAWAR_SIZE_4MB     0x00000015
#define  LAWAR_SIZE_8MB     0x00000016
#define  LAWAR_SIZE_16MB    0x00000017
#define  LAWAR_SIZE_32MB    0x00000018
#define  LAWAR_SIZE_64MB    0x00000019
#define  LAWAR_SIZE_128MB   0x0000001A
#define  LAWAR_SIZE_256MB   0x0000001B
#define  LAWAR_SIZE_512MB   0x0000001C
#define  LAWAR_SIZE_1GB     0x0000001D
#define  LAWAR_SIZE_2GB     0x0000001E

/* PCI Window SIZE  */