📄 regs.inc
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;========================================================================
; FILE: regs.inc
;
; This file contains the chip register definitions
;
;========================================================================
; I/O ports
Port0_Data: equ 00h ; GPIO data port 0
Port1_Data: equ 01h ; GPIO data port 1
Port2_Data: equ 02h ; GPIO data port 2
Port3_Data: equ 03h ; GPIO data port 3
Port0_Interrupt: equ 04h ; Interrupt enable for port 0
Port1_Interrupt: equ 05h ; Interrupt enable for port 1
Port2_Interrupt: equ 06h ; Interrupt enable for port 2
Port3_Interrupt: equ 07h ; Interrupt enable for port 3
GPIO_Config: equ 08h ; General purpose I/O configuration
; USB ports
USB_Device_Address: equ 10h ; USB device address assigned by host
EP_A0_Counter: equ 11h ; Address A endpoint 0 counter
EP_A0_Mode: equ 12h ; Address A endpoint 0 configuration
EP_A1_Counter: equ 13h ; Address A endpoint 1 counter
EP_A1_Mode: equ 14h ; Address A endpoint 1 configuration
EP_A2_Counter: equ 15h ; Address A endpoint 2 counter
EP_A2_Mode: equ 16h ; Address A endpoint 2 configuration
USB_Status_Control: equ 1Fh ; USB upstream status and control
; control ports
Global_Interrupt: equ 20h ; Global interrupt enable
Endpoint_Interrupt: equ 21h ; USB endpoint interrupt enable
Timer_LSB: equ 24h ; lower eight bits of timer
Timer_MSB: equ 25h ; upper six bits of timer
Watchdog: equ 26h ; clear watchdog Timer
; DAC port
DAC_Data: equ 30h ; GPIO DAC
DAC_Interrupt: equ 31h ; DAC interrupt enable
DAC_Interrupt_Polarity: equ 32h ; DAC interrupt polarity
DAC_Isink: equ 38h ; 4-bit sink current
DAC_Isink0: equ 38h ; bit 0
DAC_Isink1: equ 39h ; bit 1
DAC_Isink2: equ 3Ah ; bit 2
DAC_Isink3: equ 3Bh ; bit 3
DAC_Isink4: equ 3Ch ; bit 4
DAC_Isink5: equ 3Dh ; bit 5
DAC_Isink6: equ 3Eh ; bit 6
DAC_Isink7: equ 3Fh ; bit 7
; processor control port
Status_Control: equ FFh ; Processor Status and Control
RunBit: equ 1h ; CPU Run bit
SingleStep: equ 2h ; Single Step
InterruptEnable: equ 4h ; interrupt enable
SuspendWait: equ 8h ; Suspend, wait for interrupt
PowerOnReset: equ 10h ; power-on reset
USBReset: equ 20h ; USB Bus Reset bit
WatchDogReset: equ 40h ; Watchdog Reset bit
IRQpending: equ 80h ; IRQ pending
PORT0_DATA_REG: equ 00h ; GPIO data port 0
PORT1_DATA_REG: equ 01h ; GPIO data port 1
PORT2_DATA_REG: equ 02h ; GPIO data port 2
PORT3_DATA_REG: equ 03h ; GPIO data port 3
PORT0_INTERRUPT_REG: equ 04h ; Interrupt enable for port 0
PORT1_INTERRUPT_REG: equ 05h ; Interrupt enable for port 1
PORT2_INTERRUPT_REG: equ 06h ; Interrupt enable for port 2
PORT3_INTERRUPT_REG: equ 07h ; Interrupt enable for port 3
GPIO_CONFIG_REG: equ 08h ; General purpose I/O configuration
; USB ports
USB_DEVICE_ADDRESS_REG: equ 10h ; USB device address assigned by host
EP_A0_COUNTER_REG: equ 11h ; Address A endpoint 0 counter
EP_A0_MODE_REG: equ 12h ; Address A endpoint 0 configuration
EP_A1_COUNTER_REG: equ 13h ; Address A endpoint 1 counter
EP_A1_MODE_REG: equ 14h ; Address A endpoint 1 configuration
USB_STATUS_CONTROL_REG: equ 1Fh ; USB upstream status and control
; control ports
GLOBAL_INTERRUPT_REG: equ 20h ; Global interrupt enable
ENDPOINT_INTERRUPT_REG: equ 21h ; USB endpoint interrupt enable
TIMER_LSB_REG: equ 24h ; lower eight bits of timer
TIMER_MSB_REG: equ 25h ; upper six bits of timer
WATCHDOG_REG: equ 26h ; clear watchdog Timer
; DAC port
DAC_DATA_REG: equ 30h ; GPIO DAC
DAC_INTERRUPT_REG: equ 31h ; DAC interrupt enable
DAC_INTERRUPT_POLARITY_REG: equ 32h ; DAC interrupt polarity
DAC_ISINK_REG: equ 38h ; 4-bit sink current
DAC_ISINK0_REG: equ 38h ; bit 0
DAC_ISINK1_REG: equ 39h ; bit 1
DAC_ISINK2_REG: equ 3Ah ; bit 2
DAC_ISINK3_REG: equ 3Bh ; bit 3
DAC_ISINK4_REG: equ 3Ch ; bit 4
DAC_ISINK5_REG: equ 3Dh ; bit 5
DAC_ISINK6_REG: equ 3Eh ; bit 6
DAC_ISINK7_REG: equ 3Fh ; bit 7
; processor control port
STATUS_CONTROL_REG: equ FFh ; Processor Status and Control
;========================================================================
; GPIO constants
;========================================================================
; GPIO configuration
; Two bits per port the driver mode for each 8-bit port:
; 00 resistive interrupt on falling edge
; 01 CMOS no interrupts
; 10 open drain interrupt on falling edge
; 11 open drain interrupt on rising edge
PORT0_CONFIG_MASK: equ 3h ; configuration bits port 0
PORT1_CONFIG_MASK: equ 0Ch ; configuration bits port 1
PORT2_CONFIG_MASK: equ 30h ; configuration bits port 2
PORT3_CONFIG_MASK: equ C0h ; configuration bits port 3
RESISTIVE_NEG: equ FFh
CMOS_NONE: equ AAh
OPENDRAIN_NEG: equ 55h
OPENDRAIN_POS: equ 00h
;========================================================================
; USB I/O port constants
;========================================================================
; device address register
ADDRESS_MASK: equ 7Fh ; 7 bits of device address
ADDRESS_ENABLE_BIT: equ 80h ; enable the device address
; endpoint mode register
USB_MODE_MASK: equ 0Fh ; mode[3:0] bits
DISABLED: equ 0h ; disabled
NAKINOUT: equ 1h ; accept SETUP, NAK IN and OUT
STATUSOUTONLY: equ 2h ; accept SETUP and OUT, stall IN
STALL: equ 3h ; stall IN and OUT packets
SETUP: equ 4h ; accept SETUP packets
STATUSINONLY: equ 6h ; accept SETUP and IN (TX 0), stall OUT
NAKOUTSTATUSIN: equ 0Ah ; accept SETUP, NAK Out
ACKOUTSTATUSIN: equ 0Bh ; accept SETUP, TX0 IN, ACK OUT
NAKIN: equ 0Ch ; NAK IN packets
ACKIN: equ 0Dh ; ACK IN packets (EP one)
NAKIN_STATUSOUT: equ 0eh
ACKIN_STATUSOUT: equ 0Fh ; accept SETUP packets (EP zero)
; ACK IN packets
; endpoint 0 only mode register
ACK_BIT: equ 10h ; ACK received from host (same for EP1,EP2)
EP0_OUT_RCV: equ 20h ; EP0 OUT received
EP0_IN_RCV: equ 40h ; EP0 IN received
EP0_SETUP_RCV: equ 80h ; EP0 SETUP received
; endpoint count register
COUNT_MASK: equ 0Fh ; count[3:0] bits
DATAVALID: equ 40h ; data valid (OUT and SETUP)
DATATOGGLE: equ 80h ; Data 0/1 bit
; USB Status and Control
USB_CONTROL_BITS: equ 7h ; control[2:0] bits
BUS_ACTIVITY: equ 8h ; bus activity bit
DATA_BITS: equ 30h ; D+ and D-
DP: equ 20h
DM: equ 10h
DPH_DMH: equ 7
DPH_DML: equ 5
DPL_DMH: equ 6
DPL_DML: equ 3
;========================================================================
; interrupt constants
;========================================================================
; Global interrupt masks
RESET_MASK: equ 1h ; USB Bus Reset interrupt
TIMER_MASK: equ 5h ; USB Bus Reset interrupt
; one msec timer interrupt
GPIO_ONLY_MASK: equ 20h ; GPIO interrupt
TIMER_ONLY_MASK: equ 04h ; one msec timer interrupt
GPIO_TIMER_MASK: equ 24h ; GPIO and 1ms timer interrupt
GPIO_TIMER_RESET_MASK: equ 25h ; GPIO, 1ms timer and bus reset interrupt
; Global interrupt masks
GPIO_ISR_MASK: equ 20h ; GPIO interrupt
DAC_ISR_MASK: equ 10h ; DAC interrupt
TIMER_ISR_MASK: equ 04h ; one msec timer interrupt
RESET_ISR_MASK: equ 01h ; GPIO and 1ms timer interrupt
; endpoint interrupt masks
NO_ENDPOINTS: equ 0h ; no USB endpoint interrupts
ENUMERATE: equ 1h ; USB EP A0 interrupt enable
KEYBOARD_ONLY: equ 3h ; USB EP A0 interrupt enable
KEYBOARD_PLUS_MOUSE: equ 7h ; USB EP A0, A1, A2 interrupt enable
; USB EP A1 interrupt enable
EP0_EP1_EP2: equ 7h ; USB EP A0, A1, A2 interrupt enable
; USB EP A1 interrupt enable
;========================================================================
; Endpoint Interrupt Enable bits
ENDPOINT_ZERO: equ 1h ; USB EP A0 interrupt bit
ENDPOINT_ONE: equ 2h ; USB EP A1 interrupt bit
ENDPOINT_TWO: equ 4h ; USB EP A2 interrupt bit
;========================================================================
; timer constants
TIMER_MSB_MASK: equ 3Fh ; six bits
;========================================================================
; Processor Status and Control
ENTER_SUSPEND: equ 9h
RUNBIT: equ 1h ; CPU Run bit
SINGLESTEP: equ 2h ; Single Step
INTERRUPTENABLE: equ 4h ; interrupt enable
SUSPENDWAIT: equ 8h ; Suspend, wait for interrupt
POWERONRESET: equ 10h ; power-on reset
USBRESET: equ 20h ; USB Bus Reset bit
WATCHDOG_RESET: equ 40h ; Watchdog Reset bit
IRQPENDING: equ 80h ; IRQ pending
;========================================================================
; USB Status and Control
NOT_FORCING: equ 00h ; SIE controls D+/D-
FORCE_K: equ 01h ; D+ high, D- low (resume signal)
FORCE_J: equ 02h ; D+ low, D- high (idle state)
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