main.c

用ST92163开发的鼠标

#include <cpu.h>
#include <usb.h>

/*
** External Memory mapping
**
**	0		7FFF	ROM 32K 
**
**	DPR2 maps 0x30000 (first 16KB of ROM)
**	8000	BFFF	ROM
**
**	Address latching needs no address wait states
**  ROM needs 2 data wait states
*/

static void clk_init( void)
{
/*	CLOCK2 = CLOCK / 1, NO CPUCLK prescaler */
	MODER = 0 ;
	
/*	PLL = CLOCK2 * 6 / 2 */
	spp( RCCU_PG) ;
	PLLCONF &= 0xD8 ;
	PLLCONF |= 0x11 ;

	/* Wait until PLL locked */	
	while( !( CLK_FLAG & 0x02))
		;

/* Select PLL as INTCLK */		
	CLK_FLAG |= 1 ;
}

static void io_init( void)
{
/*	P0.0-7	011	AF OUT (Data/ LSB Address) */
	spp( P0C_PG) ;
	P0C0R = 0xFF ;
	P0C1R = 0xFF ;
	P0C2R = 0x00 ;

/*	P1.0-6	011	AF OUT	(MSB Address)
	P1.7	110	OUT OD	(Row1)
*/
	spp( P1C_PG) ;	/* same as P0C_PG */
	P1DR  = 0xFF ;
	P1C0R = 0x7F ;
	P1C1R = 0xFF ;
	P1C2R = 0x80 ;

/*	P3.0	000	BID	WP Schmitt Trigger	(Col0)
	P3.1	000	BID	WP Schmitt Trigger	(Col1)
	P3.2	000	BID	WP Schmitt Trigger	(Col2)
	P3.3	000	BID	WP Schmitt Trigger	(Col3)
	P3.4	000 BID WP Schmitt Trigger	(MS Data)
	P3.5	000 BID WP Schmitt Trigger	(MS CLK)
	P3.6	011	AF OUT	(ALE)
	P3.7	110	OUT OD	(Row0)
*/
	spp( P3C_PG) ;
	P3DR = 0xFF ;
    P3C0R = 0x40 ;	
    P3C1R = 0xC0 ;
    P3C2R = 0x80 ;

/*	P4.0	000	BID	WP Schmitt Trigger	(Col4)
	P4.1	000	BID	WP Schmitt Trigger	(Col5)
	P4.2	000	BID	WP Schmitt Trigger	(Col6)
	P4.3	000	BID	WP Schmitt Trigger	(Col7)
*/
	spp( P4C_PG) ;
	P4DR = 0xFF ;
	P4C0R = 0x00 ;
	P4C1R = 0x00 ;		
	P4C2R = 0x00 ;

/*	P5.0-7	110	OUT PP (Row8-15)
*/
	spp( P5C_PG) ;
	P5DR = 0xFF ;
	P5C0R = 0x00 ;
	P5C1R = 0xFF ;
	P5C2R = 0xFF ;

/*	P6.0	110	OUT OD	(Row7)
	P6.1	110	OUT OD	(Row6)
	P6.2	110	OUT OD	(Row5)
	P6.3	110	OUT OD	(Row4)
	P6.4	110	OUT OD	(Row3)
	P6.5	110	OUT OD	(Row2)
	P6.6	111	AF IN	(Joy_X)
	P6.7	111	AF IN	(Joy_Y)
*/
	spp( P6C_PG) ;
	P6DR = 0xFF ;
	P6C0R = 0xC0 ;	
	P6C1R = 0xFF ;		
	P6C2R = 0xFF ;

	spp( 21);
	DPR2_P = 0x0D ;	/* DPR2 -> 0x34000 */
	EMR1 = 0x50 ; // 0xC2 ;	/* MC ASAF BSZ */
	EMR2 = 0x10 ;	/* MEMSEL, no address stretch */

	spp( 0) ;
	WCR = 0x42 ;	/* WD disabled + 2 wait states for the lower ext memory area */

	spp( 21) ;
	DPR2_P = 0x0D ;	/* DPR2 -> 0x34000 */
	if( *((WORD *) 0xBFFE) == 0x55AA)
	{
		spp( 21) ;
		DPR2_P = 0x0C ;	/* DPR2 -> 0x30000 */
		/* Jump after the interrupt vector table */
		asm( "ldw rr0, 0x8000") ;
		asm( "pushw rr0") ;
		asm( "push #3") ;
		asm( "rets") ;
	}

	spp( FAD_PG) ;
	FAD_CLR = 0x94 ; /* Power up the A/D converter (Slow mode) */
	FAD_CLR = 0xA4 ; /* Power up the A/D converter (Slow mode) */
}

BYTE	error ;
WORD	tmp ;
BYTE	mancode ;
BYTE	devcode ;

void tests( void)
{
	WORD	*p ;
	BYTE	*pb ;

/* Check first segment of ROM */
	pb = (BYTE *) 0x8000 ;
	tmp = 0 ;
	while( pb < (BYTE *) 0xC000)
	{
		tmp +=  *pb ;
		pb++ ;
	}

	if( tmp != 0x92C7)
		error |= 2 ;
}

void main( void)
{
	BYTE	i, cnt = 0 ;
	
	io_init() ;
	clk_init() ;
//	tests() ;

	isr_init() ;
	Get_Connection0() ;

	for( ;;)
	{
		HUB_proc() ;
		KEYBOARD_proc() ;
		MOUSE_proc() ;
		JOYSTICK_proc() ;
	}
}

/* end of main.c */