copy of st92163.inc

用ST92163开发的鼠标

s_rdapr  = r1                   ; receive DMA address pointer register
S_TDCPR := R242                 ; transmit DMA counter pointer register
s_tdcpr  = r2                   ; transmit DMA counter pointer register
S_TDAPR := R243                 ; transmit DMA address pointer register
s_tdapr  = r3                   ; transmit DMA address pointer register

S_IVR   := R244                 ; interrupt vector register
s_ivr    = r4                   ; interrupt vector register

S_ACR   := R245                 ; address compare register
s_acr    = r5                   ; address compare register

S_IMR   := R246                 ; interrupt mask register
s_imr    = r6                   ; interrupt mask register
.defstr S_txdi  "s_imr.0"	; transmitter data interrupt
.defstr S_rxdi  "s_imr.1"	; receiver data interrupt
.defstr S_rxb   "s_imr.2"	; receiver break
.defstr S_rxa   "s_imr.3"	; receiver address
.defstr S_rxe   "s_imr.4"	; receiver error
.defstr S_txeob "s_imr.5"	; transmit end of block
.defstr S_rxeob "s_imr.6"	; receive end of block
.defstr S_bsn   "s_imr.7"	; Buffer or shift register empty.
Sm_txdi  := ( 1 <- 0 )		; transmitter data interrupt mask
Sm_rxdi  := ( 1 <- 1 )		; receiver data interrupt mask
Sm_rxb   := ( 1 <- 2 )		; receiver break mask
Sm_rxa   := ( 1 <- 3 )		; receiver address mask
Sm_rxe   := ( 1 <- 4 )		; receiver error mask
Sm_txeob := ( 1 <- 5 )		; transmit end of block mask
Sm_rxeob := ( 1 <- 6 )		; receive end of block mask
Sm_bsn   := ( 1 <- 7 )		; Buffer or shift register empty mask.

S_ISR   := R247                 ; interrupt status register
s_isr    = r7                   ; interrupt status register
.defstr S_txsem "s_isr.0"	; transmit shift register empty
.defstr S_txbem "s_isr.1"	; transmit buffer register empty
.defstr S_rxdp  "s_isr.2"	; received data pending bit
.defstr S_rxbp  "s_isr.3"	; received break pending bit
.defstr S_rxap  "s_isr.4"	; received address pending bit
.defstr S_pe    "s_isr.5"	; parity error pending bit
.defstr S_fe    "s_isr.6"	; framing error pending bit
.defstr S_oe    "s_isr.7"	; overrun error pending bit
Sm_txsem := ( 1 <- 0 )		; transmit shift register empty mask
Sm_txbem := ( 1 <- 1 )		; transmit buffer register empty mask
Sm_rxdp  := ( 1 <- 2 )		; received data pending mask
Sm_rxbp  := ( 1 <- 3 )		; received break pending mask
Sm_rxap  := ( 1 <- 4 )		; received address pending mask
Sm_pe    := ( 1 <- 5 )		; parity error pending mask
Sm_fe    := ( 1 <- 6 )		; framing error pending mask
Sm_oe    := ( 1 <- 7 )		; overrun error pending mask

S_RXBR  := R248                 ; receive buffer register
s_rxbr   = r8                   ; receive buffer register

S_TXBR  := R248                 ; transmit buffer register
s_txbr   = r8                   ; transmit buffer register

S_IDPR  := R249                 ; interrupt/DMA priority register
s_idpr   = r9                   ; interrupt/DMA priority register
.defstr S_txd  "s_idpr.3"	; transmitter DMA
.defstr S_rxd  "s_idpr.4"	; receiver DMA
.defstr S_sa   "s_idpr.5"	; set address
.defstr S_sb   "s_idpr.6"	; set break
.defstr S_amen "s_idpr.7"	; address mode enable
Sm_pri  := 07h			; interrupt/DMA priority mask
Sm_txd  := ( 1 <- 3 )		; transmitter DMA mask
Sm_rxd  := ( 1 <- 4 )		; receiver DMA mask
Sm_sa   := ( 1 <- 5 )		; set address mask
Sm_sb   := ( 1 <- 6 )		; set break mask
Sm_amen := ( 1 <- 7 )		; address mode enable mask

S_CHCR  := R250                 ; Character configuration register
s_chcr   = r10                  ; Character configuration register
.defstr S_ab   "s_chcr.4"	; Address/9th bit
.defstr S_pen  "s_chcr.5"	; Parity enable
.defstr S_ep   "s_chcr.6"	; Even parity
.defstr S_am   "s_chcr.7"	; Address mode
  
Sm_wl5  := 000h			; 5 bits data word mask
Sm_wl6  := 001h			; 6 bits data word mask
Sm_wl7  := 002h			; 7 bits data word mask
Sm_wl8  := 003h			; 8 bits data word mask

Sm_sb10 := 000h			; 1.0 stop bit mask
Sm_sb15 := 004h			; 1.5 stop bit mask
Sm_sb20 := 008h			; 2.0 stop bit mask
Sm_sb25 := 00Ch			; 2.5 stop bit mask

Sm_ab   := 010h			; address bit insertion mask
Sm_pen  := 020h			; parity enable mask
Sm_ep   := 040h			; Even parity mask
Sm_oddp := 000h			; odd parity mask
Sm_am   := 080h			; address mode mask

S_CCR   := R251                 ; Clock configuration register
s_ccr    = r11                  ; Clock configuration register
.defstr S_stpen "s_ccr.0"	; stick parity enable
.defstr S_lben  "s_ccr.1"	; loop back enable
.defstr S_aen   "s_ccr.2"	; auto echo enable
.defstr S_cd    "s_ccr.3"	; Clock divider
.defstr S_xbrg  "s_ccr.4"	; External baud rate generator source
.defstr S_xrx   "s_ccr.5"	; External receiver source
.defstr S_oclk  "s_ccr.6"	; output clock selection
.defstr S_xtclk "s_ccr.7"	; transmit clock selection
Sm_stpen := ( 1 <- 0 )          ; stick parity enable mask
Sm_lben  := ( 1 <- 1 )          ; loop back enable mask
Sm_aen   := ( 1 <- 2 )          ; auto echo enable mask
Sm_cd    := ( 1 <- 3 )          ; Clock divider mask
Sm_xbrg  := ( 1 <- 4 )          ; External baud rate generator source mask
Sm_xrx   := ( 1 <- 5 )          ; External receiver source mask
Sm_oclk  := ( 1 <- 6 )          ; output clock selection mask
Sm_xtclk := ( 1 <- 7 )          ; transmit clock selection mask

S_BRGR  := RR252                ; baud rate generator register
s_brgr   = rr12                 ; baud rate generator register
S_BRGHR := R252                 ; baud rate generator reg. high
s_brghr  = r12                  ; baud rate generator reg. high
S_BRGLR := R253                 ; baud rate generator reg. low
s_brglr  = r13                  ; baud rate generator reg. low

S_SICR  := R254                 ; Synchronous input control register
s_sicr   = r14                  ; Synchronous input control register
.defstr S_inpen "s_sicr.2"      ; All input disable
.defstr S_dcdpl "s_sicr.3"      ; DCD input polarity
.defstr S_dcden "s_sicr.4"      ; DCD input enable
.defstr S_xckpl "s_sicr.5"      ; Receiver clock polarity
.defstr S_inpl  "s_sicr.6"      ; SIN input polarity
.defstr S_smen  "s_sicr.7"      ; Synchronous mode enable
Sm_inpen := ( 1 <- 2 )          ; All input disable mask
Sm_dcdpl := ( 1 <- 3 )          ; DCD input polarity mask
Sm_dcden := ( 1 <- 4 )          ; DCD input enable mask
Sm_xckpl := ( 1 <- 5 )          ; Receiver clock polarity mask
Sm_inpl  := ( 1 <- 6 )          ; SIN input polarity mask
Sm_smen  := ( 1 <- 7 )          ; Synchronous mode enable mask

S_SOCR  := R255                 ; Synchronous output control register
s_socr   = r15                  ; Synchronous output control register
.defstr S_ctspl "s_socr.2"      ; CTS output polarity 
.defstr S_ctsen "s_socr.3"      ; CTS output enable
.defstr S_ocksb "s_socr.4"      ; Transmitter clock stand-by level
.defstr S_ockpl "s_socr.5"      ; Transmitter clock polarity
.defstr S_outsb "s_socr.6"      ; SOUT output stand-by level
.defstr S_outpl "s_socr.7"      ; SOUT output polarity
Sm_ctspl := ( 1 <- 2 )          ; CTS output polarity mask
Sm_ctsen := ( 1 <- 3 )          ; CTS output enable mask
Sm_ocksb := ( 1 <- 4 )          ; Transmitter clock stand-by level mask
Sm_ockpl := ( 1 <- 5 )          ; Transmitter clock polarity mask
Sm_outsb := ( 1 <- 6 )          ; SOUT output stand-by level mask
Sm_outpl := ( 1 <- 7 )          ; SOUT output polarity mask

MIRROR_PG := 60                 ; Mirrir control registers page
MIRRA   := R246                 ; mirror register 
MIRRB   := R247                 ; mirror register 

;*************************
;* MMU Control Registers *
;*************************
; MMU data page registers located in 
; System Group E (bit DPRREM=1 in EMR2 register)

DPR0	:= R224
dpr0	:= r0
DPR1	:= R225
dpr1	:= r1
DPR2	:= R226
dpr2	:= r2
DPR3	:= R227
dpr3	:= r3

; MMU data page registers located in 
; the page 21 (bit DPRREM=0 in EMR2 register)

MMU_PG	:= 21

DPR0_P	:= R240
dpr0_p   = r0
DPR1_P	:= R241
dpr1_p   = r1
DPR2_P	:= R242
dpr2_p   = r3
DPR3_P	:= R243
dpr3_p   = r4

CSR	:= R244			; MMU code segment register
csr      = r4
ISR	:= R248			; MMU interrupt segment register
isr      = r8
DMASR	:= R249			; MMU DMA segment register
dmasr    = r6

EMR1	:= R245			; MMU configuration registers
emr1     = r5
.defstr mc       "emr1.6"       ; mode control
.defstr ds2n     "emr1.5"       ; data strobe 2 enable
.defstr asaf     "emr1.4"       ; address strobe as alternate function
.defstr nmb      "emr1.3"       ; no multiplexed bus
.defstr eto      "emr1.2"       ; external toggle
.defstr bsz      "emr1.1"       ; bus size
.defstr romless  "emr1.0"       ; romless
EMR1_mc      := ( 1 <- 6 )      ; mode control
EMR1_ds2n    := ( 1 <- 5 )      ; data strobe 2 enable
EMR1_asaf    := ( 1 <- 4 )      ; address strobe as alternate function
EMR1_nmb     := ( 1 <- 3 )      ; no multiplexed bus
EMR1_eto     := ( 1 <- 2 )      ; external toggle
EMR1_bsz     := ( 1 <- 1 )      ; bus size
EMR1_romless := ( 1 <- 0 )      ; romless

EMR2	:= R246
emr2     = r6
.defstr bromless "emr2.7"       ; Boot-Romless
.defstr encsr    "emr2.6"       ; ENable Code Segment register
.defstr dprrem   "emr2.5"       ; data Page register Remapped
.defstr memsel   "emr2.4"       ; MEMory SELect
.defstr las1     "emr2.3"       ; Lower memory Address strobe Stretch bit 1
.defstr las0     "emr2.2"       ; Lower memory Address strobe Stretch bit 0
.defstr uas1     "emr2.1"       ; Upper memory Address strobe Stretch bit 1
.defstr uas0     "emr2.0"       ; Upper memory Address strobe Stretch bit 0
EMR2_bromless := ( 1 <- 7 )     ; Boot-Romless
EMR2_encsr    := ( 1 <- 6 )     ; ENable Code Segment register
EMR2_dprrem   := ( 1 <- 5 )     ; data Page register Reapped
EMR2_memsel   := ( 1 <- 4 )     ; MEMory SELect
EMR2_las      := ( 3 <- 2 )     ; Lower memory Address strobe Stretch
EMR2_uas      := ( 3 <- 0 )     ; Upper memory Address strobe stretch

;**************************
;* RCCU Control Registers *
;**************************

RCCU_PG := 55                   ; RCCU registers page

CLKCTL	:= R240                 ; Clock Control register 
clkctl   = r0                   ; Clock Control register 
.defstr lpowfi   "clkctl.0"     ; Low Power Mode during WFI bit
.defstr wficksel "clkctl.1"     ; WFI clock select bit
.defstr ckafsel  "clkctl.2"     ; Alternate Function Clock Select bit
.defstr sresen   "clkctl.3"     ; HALT command bit
.defstr intsel   "clkctl.7"     ; Interrupt selection bit
Cm_lpowfi   := ( 1 <- 0 )       ; Low Power Mode during Wait for interrupt
Cm_wficksel := ( 1 <- 1 )       ; WFI Clock select
Cm_ckafsel  := ( 1 <- 2 )       ; Alternate Function Clock Select
Cm_sresen   := ( 1 <- 3 )       ; HALT command  
Cm_intsel   := ( 1 <- 7 )       ; Interrupt selection 

CLK_FLAG := R242		; Clock Flag register 
clk_flag  = r2			; Clock Flag register 
.defstr csucksel "clk_flag.0"   ; System Clock Selection bit
.defstr lock     "clk_flag.1"   ; System Clock lock flag
.defstr ckafst   "clk_flag.2"   ; Flag for Alternate Function Clock bit
.defstr xtdiv16  "clk_flag.3"   ; CLOCK2/16 selection bit
.defstr xtstop   "clk_flag.4"   ; Xtal oscillator Stop bit
.defstr softres  "clk_flag.5"   ; Software Reset flag bit
.defstr wdgres   "clk_flag.6"   ; Watchdog Reset flag bit
.defstr exstp    "clk_flag.7"   ; External stop flag bit
Cm_csucksel := ( 1 <- 0 )       ; System Clock selection
Cm_lock     := ( 1 <- 1)        ; System Clock lock flag
Cm_ckafst   := ( 1 <- 2 )       ; Flag for alternate function clock
Cm_xtdiv16  := ( 1 <- 3 )       ; CLOCK2/16 selection
Cm_xtstop   := ( 1 <- 4 )       ; Xtal oscillator stop
Cm_softres  := ( 1 <- 5 )       ; Software reset flag
Cm_wdgres   := ( 1 <- 6 )       ; Watchdog reset flag
Cm_exstp    := ( 1 <- 7 )       ; external stop flag

PLLCONF := R246			; PLL configuration register 
pllconf := r6			; PLL configuration register 

Cm_mul14  := 020h               ; PLL multiplication factor : 14
Cm_mul10  := 000h               ; PLL multiplication factor : 10
Cm_mul8   := 030h               ; PLL multiplication factor : 8
Cm_mul6   := 010h               ; PLL multiplication factor : 6

Cm_div1   := 000h               ; PLL divider factor : 1
Cm_div2   := 001h               ; PLL divider factor : 2
Cm_div3   := 002h               ; PLL divider factor : 3
Cm_div4   := 003h               ; PLL divider factor : 4
Cm_div5   := 004h               ; PLL divider factor : 5
Cm_div6   := 005h               ; PLL divider factor : 6
Cm_div7   := 006h               ; PLL divider factor : 7
Cm_plloff := 007h               ; PLL OFF 

.list

;***************************** end of file **********************************/