copy of st92163.inc

用ST92163开发的鼠标

T_CMP0HR := R244                ; Compare 0 high register
t_cmp0hr  = r4
T_CMP0LR := R245                ; Compare 0 low register
t_cmp0lr  = r5

T_CMP1R := RR246                ; MFTimer CMP1 store compare constant.
t_cmp1r  = rr6
T_CMP1HR := R246                ; Compare 1 high register
t_cmp1hr  = r6
T_CMP1LR := R247                ; Compare 1 low register
t_cmp1lr  = r7

T_TCR	:= R248                 ; MFTimer Control Register.
t_tcr    = r8
.defstr T_cs    "t_tcr.0"	; Counter status
.defstr T_of0   "t_tcr.1"	; over/underflow on CAP on REG0
.defstr T_udcs  "t_tcr.2"	; up/down count status
.defstr T_udc   "t_tcr.3"	; up/down count
.defstr T_ccl   "t_tcr.4"	; Counter clear
.defstr T_ccmp0 "t_tcr.5"	; Clear on compare 0
.defstr T_ccp0  "t_tcr.6"	; Clear on capture
.defstr T_cen   "t_tcr.7"	; Counter enable        
Tm_cs    := ( 1 <- 0 )		; Counter status mask
Tm_of0   := ( 1 <- 1 )		; over/underflow mask on CAP on REG0
Tm_udcs  := ( 1 <- 2 )		; up/down count status mask
Tm_udc   := ( 1 <- 3 )		; up/down count mask
Tm_ccl   := ( 1 <- 4 )		; Counter clear mask
Tm_ccmp0 := ( 1 <- 5 )		; Clear on compare mask
Tm_ccp0  := ( 1 <- 6 )		; Clear on capture mask
Tm_cen   := ( 1 <- 7 )		; Counter enable mask

T_TMR   := R249                 ; MFTimer Mode Register.
t_tmr    = r9
.defstr T_co  "t_tmr.0"		; Continuous/one shot bit
.defstr T_ren "t_tmr.1"		; retrigger enable bit
.defstr T_eck "t_tmr.2"		; Enable clocking mode bit
.defstr T_rm0 "t_tmr.3"		; register 0 mode bit
.defstr T_rm1 "t_tmr.4"		; register 1 mode bit
.defstr T_bm  "t_tmr.5"		; bivalue mode bit
.defstr T_oe0 "t_tmr.6"		; output 0 enable bit
.defstr T_oe1 "t_tmr.7"		; output 1 enable bit
Tm_co   := ( 1 <- 0 )		; Continuous/one shot mask
Tm_ren  := ( 1 <- 1 )		; retrigger enable mask
Tm_eck  := ( 1 <- 2 )		; Enable clocking mode mask
Tm_rm0  := ( 1 <- 3 )		; register 0 mode mask
Tm_rm1  := ( 1 <- 4 )		; register 1 mode mask
Tm_bm   := ( 1 <- 5 )		; bivalue mode mask
Tm_oe0  := ( 1 <- 6 )		; output 0 enable mask
Tm_oe1  := ( 1 <- 7 )		; output 1 enable mask

T_ICR   := R250                 ; MFTimer External Input Control Register.
t_icr    = r10

Tm_exb_f   := 01h               ; External B falling edge sensitive mask
Tm_exb_r   := 02h               ; External B rising edge sensitive mask
Tm_exb_rf  := 03h               ; External B falling and rising edge mask
Tm_exa_f   := 04h               ; External A falling edge sensitive mask
Tm_exa_r   := 08h               ; External A rising edge sensitive mask
Tm_exa_rf  := 0Ch               ; External A falling and rising edge mask
Tm_ab_ii   := 00h               ; A I/O B I/O mask
Tm_ab_it   := 10h               ; A I/O B trigger mask
Tm_ab_gi   := 20h               ; A gate B I/O mask
Tm_ab_gt   := 30h               ; A gate B trigger mask
Tm_ab_ie   := 40h               ; A I/O B external clock mask
Tm_ab_ti   := 50h               ; A trigger B I/O mask
Tm_ab_ge   := 60h               ; A gate B external clock mask
Tm_ab_tt   := 70h               ; A trigger B trigger mask
Tm_ab_cucd := 80h               ; A clock up B clock down mask
Tm_ab_ue   := 90h               ; A clock up/down B external clock mask
Tm_ab_tutd := 0A0h              ; A trigger up B trigger down mask
Tm_ab_ui   := 0B0h              ; A up/down clock B I/O mask
Tm_ab_aa   := 0C0h              ; A autodiscr. B autodiscr. mask
Tm_ab_te   := 0D0h              ; A trigger B external clock mask
Tm_ab_et   := 0E0h              ; A external clock B trigger mask
Tm_ab_tg   := 0F0h              ; A trigger B gate mask

T_PRSR  := R251                 ; MFTimer prescaler register
t_prsr   = r11

T_OACR  := R252                 ; MFTimer Output A Control Register.
t_oacr   = r12
Tm_cev     := 02h		; on chip event bit on COMPARE 0 mask

T_OBCR  := R253                 ; MFTimer Output B Control Register.
t_obcr   = r13
Tm_op      := 01h               ; output preset bit mask
Tm_oev     := 02h               ; on chip event bit on OVF/UDF mask
Tm_ou_set  := 00h               ; overflow underflow set mask
Tm_ou_tog  := 04h               ; overflow underflow toggle mask
Tm_ou_res  := 08h               ; overflow underflow reset mask
Tm_ou_nop  := 0Ch               ; overflow underflow nop mask
Tm_c1_set  := 00h               ; Compare 1 set mask
Tm_c1_tog  := 10h               ; Compare 1 toggle mask
Tm_c1_res  := 20h               ; Compare 1 reset mask
Tm_c1_nop  := 30h               ; Compare 1 nop mask
Tm_c0_set  := 00h               ; Compare 0 set mask
Tm_c0_tog  := 40h               ; Compare 0 toggle mask
Tm_c0_res  := 80h               ; Compare 0 reset mask
Tm_c0_nop  := 0C0h              ; Compare 0 nop mask

T_FLAGR := R254                 ; MFTimer Flags Register.
t_flagr  = r14
.defstr T_ao   "t_flagr.0"	; and/or on capture interrupt
.defstr T_ocm0 "t_flagr.1"	; overrun compare 0
.defstr T_ocp0 "t_flagr.2"	; overrun capture 0
.defstr T_ouf  "t_flagr.3"	; overflow underflow flag
.defstr T_cm1  "t_flagr.4"	; successful compare 1
.defstr T_cm0  "t_flagr.5"	; successful compare 0
.defstr T_cp1  "t_flagr.6"	; successful capture 1 
.defstr T_cp0  "t_flagr.7"	; successful capture 0
Tm_ao   := ( 1 <- 0 )		; and/or on capture interrupt mask
Tm_ocm0 := ( 1 <- 1 )		; overrun compare 0 mask
Tm_ocp0 := ( 1 <- 2 )		; overrun capture 0 mask
Tm_ouf  := ( 1 <- 3 )		; overflow underflow flag mask
Tm_cm1  := ( 1 <- 4 )		; successful compare 1 mask
Tm_cm0  := ( 1 <- 5 )		; successful compare 0 mask
Tm_cp1  := ( 1 <- 6 )		; successful capture 1 mask
Tm_cp0  := ( 1 <- 7 )		; successful capture 0 mask

T_IDMR  := R255                 ; MFTimer Interrupt DMA Mask Register.
t_idmr   = r15
.defstr T_oui   "t_idmr.0"	; overflow underflow interrupt
.defstr T_cm1i  "t_idmr.1"	; Compare 1 interrupt
.defstr T_cm0i  "t_idmr.2"	; Compare 0 interrupt
.defstr T_cm0d  "t_idmr.3"	; Compare 0 DMA
.defstr T_cp1i  "t_idmr.4"	; Capture 1 interrupt
.defstr T_cp0i  "t_idmr.5"	; Capture 0 interrupt
.defstr T_cp0d  "t_idmr.6"	; Capture 0 DMA
.defstr T_gtien "t_idmr.7"	; global timer interrupt enable
Tm_oui   := ( 1 <- 0 )		; overflow underflow interrupt mask
Tm_cm1i  := ( 1 <- 1 )		; Compare 1 interrupt mask
Tm_cm0i  := ( 1 <- 2 )		; Compare 0 interrupt mask
Tm_cm0d  := ( 1 <- 3 )		; Compare 0 DMA mask
Tm_cp1i  := ( 1 <- 4 )		; Capture 1 interrupt mask
Tm_cp0i  := ( 1 <- 5 )		; Capture 0 interrupt mask
Tm_cp0d  := ( 1 <- 6 )		; Capture 0 DMA mask
Tm_gtien := ( 1 <- 7 )		; global timer interrupt enable mask

T0_DCPR := R240                 ; MFTimer 0 DMA Counter Pointer Register.
t0_dcpr  = r0
T1_DCPR := R244                 ; MFTimer 1 DMA Counter Pointer Register.
t1_dcpr  = r4
T0_DAPR := R241                 ; MFTimer 0 DMA Address Pointer Register.
t0_dapr  = r1
T1_DAPR := R245                 ; MFTimer 1 DMA Address Pointer Register.
t1_dapr  = r5
T0_IVR  := R242                 ; MFTimer 0 Interrupt Vector Register.
t0_ivr   = r2
T1_IVR  := R246                 ; MFTimer 1 Interrupt Vector Register.
t1_ivr   = r6
T0_IDCR := R243                 ; MFTimer 0 Interrupt/DMA Control Register.
t0_idcr  = r3
T1_IDCR := R247                 ; MFTimer 1 Interrupt/DMA Control Register.
t1_idcr  = r7

T2_DCPR := R240                 ; MFTimer 2 DMA Counter Pointer Register.
t2_dcpr  = r0
T3_DCPR := R244                 ; MFTimer 3 DMA Counter Pointer Register.
t3_dcpr  = r4
T2_DAPR := R241                 ; MFTimer 2 DMA Address Pointer Register.
t2_dapr  = r1
T3_DAPR := R245                 ; MFTimer 3 DMA Address Pointer Register.
t3_dapr  = r5
T2_IVR  := R242                 ; MFTimer 2 Interrupt Vector Register.
t2_ivr   = r2
T3_IVR  := R246                 ; MFTimer 3 Interrupt Vector Register.
t3_ivr   = r6
T2_IDCR := R243                 ; MFTimer 2 Interrupt/DMA Control Register.
t2_idcr  = r3
T3_IDCR := R247                 ; MFTimer 3 Interrupt/DMA Control Register.
t3_idcr  = r7

Tm_plm  := 07h			; Priority level mask
Tm_swen := 08h			; Swap function enable mask
Tm_dctd := 10h			; DMA compare transaction destination mask
Tm_dcts := 20h			; DMA capture transaction source mask
Tm_cme  := 40h			; Compare 0 end of block mask
Tm_cpe  := 80h			; Capture 0 end of block mask

T_IOCR  := R248                 ; MFTimer I/O connection register
t_iocr   = r8
Tm_sc0  := 01h                  ; TxOUTA and TxINA for even MFTimer
Tm_sc1  := 02h                  ; TxOUTA and TxINA for odd MFTimer

;****************************
;* Standard Timer Registers *
;****************************

ST_PG   := 11                   ; Standard Timer registers page

ST_HR   := R240                 ; counter high value register
st_hr    = r0                   ; counter high value register
ST_LR   := R241                 ; counter low value register
st_lr    = r1                   ; counter low value register
ST_PR   := R242                 ; prescaler value register
st_pr    = r2                   ; prescaler value register

ST_CR   := R243                 ; control register
st_cr    = r3                   ; control register
.defstr ST_ints  "st_cr.2"	; interrupt select
.defstr ST_inen  "st_cr.3"	; input enable bit
.defstr ST_cont  "st_cr.6"	; single/continuos bit
.defstr ST_st    "st_cr.7"	; start/stop bit
STm_out   := ( 3 <- 0 )		; output selection mask
STm_ints  := ( 1 <- 2 )		; interrupt select mask
STm_inpen := ( 1 <- 3 )		; input enable mask
STm_inpmd := ( 3 <- 4 )		; input mode mask
STm_s_c   := ( 1 <- 6 )		; single/continuous mode mask
STm_st_sp := ( 1 <- 7 )		; start/stop mask

STm_out_dis      := 000h        ; output disabled
STm_out_square   := 001h        ; output square wave, toggle at end of count
STm_out_0        := 002h        ; output 0 at end of count
STm_out_1        := 003h        ; output 1 at end of count
STm_inpts_slim   := 000h        ; standard timer interrupt
STm_inpts_ext    := 004h        ; external interrupt
STm_inpen_dis    := 000h        ; input section disable
STm_inpen_en     := 008h        ; input section enable
STm_inpmd_evt    := 000h        ; event counter input mode
STm_inpmd_gate   := 010h        ; gated input mode 
STm_inpmd_trig   := 020h        ; triggerable input mode
STm_inpmd_retrig := 030h        ; retriggerable input mode
STm_s_c_cont     := 000h        ; continuous mode
STm_s_c_single   := 040h        ; single mode
STm_st_sp_stop   := 000h        ; stop standard timer
STm_st_sp_start  := 080h        ; start standard timer

;***************************************************************************

;               ST9 FAMILY FAST A/D CONVERTER REGISTERS.

;***************************************************************************

FAD_PG  := 62                   ; A/D converter registers page

FAD_DTR := R240                 ; data register
fad_dtr  = r0                   ; data register
FAD_CLR := R241                 ; Control logic register
fad_clr  = r1                   ; Control logic register

  .defstr FAD_str  "fad_clr.0"  ; start/stop bit
  .defstr FAD_cont "fad_clr.1"  ; Continuous mode
  .defstr FAD_pow  "fad_clr.2"  ; power enable/disable control
  .defstr FAD_trg  "fad_clr.3"  ; external trigger selection
  .defstr FAD_fs   "fad_clr.4"  ; fast/slow mode

FADm_str     := ( 1 <- 0 )      ; start/stop bit mask
FADm_cont    := ( 1 <- 1 )      ; Continuous mode mask
FADm_pow     := ( 1 <- 2 )      ; power enable/disable control mask
FADm_trg     := ( 1 <- 3 )      ; external trigger enable/disable mask
FADm_fs      := ( 1 <- 4 )      ; fast/slow mode mask
FADm_channel := ( 7 <- 5 )      ; channel number

FADm_str_stop        := 000h    ; stop conversion
FADm_str_start       := 001h    ; start conversion
FADm_cont_single     := 000h    ; single conversion
FADm_cont_cont       := 002h    ; continuous conversion
FADm_pow_dis         := 000h    ; power disable
FADm_pow_en          := 004h    ; power enable
FADm_trg_dis         := 000h    ; external trigger disable
FADm_trg_en          := 008h    ; external trigger (falling edge) enable
FADm_fs_fast         := 000h    ; fast conversion mode
FADm_fs_slow         := 010h    ; slow conversion mode

FAD_INT := R242                 ; AD interrupt register
fad_dtr  = r2                   ; AD interrupt register

  .defstr FAD_ad_int  "fad_int.0"  ; ADC interrupt select bit

FADm_ad_int     := ( 1 <- 0 )      ; ADC interrupt select bit mask

;********************************************
;* Serial Communication Interface Registers *
;********************************************

SCI0_PG := 24                   ; SCI0 control registers page
SCI1_PG := 25                   ; SCI1 control registers page
SCI2_PG := 26                   ; SCI2 control registers page
SCI3_PG := 27                   ; SCI3 control registers page

S_RDCPR := R240                 ; receive DMA counter pointer register
s_rdcpr  = r0                   ; receive DMA counter pointer register
S_RDAPR := R241                 ; receive DMA address pointer register