copy of st92163.inc

用ST92163开发的鼠标

WDm_inm_t   := 020h             ; TWD input mode triggerable.
WDm_inm_rt  := 030h             ; TWD input mode retriggerable.

WCR	:= R252			; Wait control register
wcr	 = r12
.defstr WD_wden  "wcr.6"        ; TWD timer enable.
.defstr uds2     "wcr.5"        ; Upper memory Address strobe Stretch bit 2
.defstr uds1     "wcr.4"        ; Upper memory Address strobe Stretch bit 1
.defstr uds0     "wcr.3"        ; Upper memory Address strobe Stretch bit 0
.defstr lds2     "wcr.2"        ; Lower memory Address strobe Stretch bit 2
.defstr lds1     "wcr.1"        ; Lower memory Address strobe Stretch bit 1
.defstr lds0     "wcr.0"        ; Lower memory Address strobe Stretch bit 0
Wm_wdgen := ( 1 <- 6 )          ; TWD timer enable mask
Wm_uds2  := ( 1 <- 5 )          ; Upper Memory Data Strobe Wait Cycle
Wm_uds1  := ( 1 <- 4 )
Wm_uds0  := ( 1 <- 3 )
Wm_lds2  := ( 1 <- 2 )          ; Lower Memory Data Strobe Wait Cycle
Wm_lds1  := ( 1 <- 1 )
Wm_lds0  := ( 1 <- 0 )

WCR_uds  := ( 7 <- 3 )          ; Upper memory Address strobe Stretch
WCR_lds  := ( 7 <- 0 )          ; Lower memory Address strobe stretch

Wm_umwc1 := Wm_uds0             ; 1 wait cycle  on upper M.
Wm_umwc2 := Wm_uds1             ; 2 wait cycles on upper M.
Wm_umwc3 := ( Wm_uds1|Wm_uds0 ) ; 3 wait cycles on upper M.
Wm_umwc4 := Wm_uds2             ; 4 wait cycles on upper M.
Wm_umwc5 := (Wm_uds2|Wm_uds0)   ; 5 wait cycles on upper M.
Wm_umwc6 := (Wm_uds2|Wm_uds1)   ; 6 wait cycles on upper M.
Wm_umwc7 := (Wm_uds2|Wm_uds1|Wm_uds0) ; 7 wait cycles on upper M.

Wm_lmwc1 :=  Wm_lds0            ; 1 wait cycle  on lower M.
Wm_lmwc2 :=  Wm_lds1            ; 2 wait cycles on lower M.
Wm_lmwc3 := (Wm_lds1|Wm_lds0 )  ; 3 wait cycles on lower M.
Wm_lmwc4 :=  Wm_lds2            ; 4 wait cycles on lower M.
Wm_lmwc5 := (Wm_lds2|Wm_lds0 )  ; 5 wait cycles on lower M.
Wm_lmwc6 := (Wm_lds2|Wm_lds1 )  ; 6 wait cycles on lower M.
Wm_lmwc7 := (Wm_lds2|Wm_lds1|Wm_lds0) ; 7 wait cycles on lower M.

; for ST9OLD

Wm_wdm2  := ( 1 <- 5 )          ; Data Memory Wait Cycle
Wm_wdm1  := ( 1 <- 4 ) 
Wm_wdm0  := ( 1 <- 3 )
Wm_wpm2  := ( 1 <- 2 )          ; Program Memory Wait Cycle
Wm_wpm1  := ( 1 <- 1 )
Wm_wpm0  := ( 1 <- 0 )

Wm_dmwc1 := Wm_wdm0             ; 1 wait cycle  on Data M.
Wm_dmwc2 := Wm_wdm1             ; 2 wait cycles on Data M.
Wm_dmwc3 := ( Wm_wdm1|Wm_wdm0 ) ; 3 wait cycles on Data M.
Wm_dmwc4 := Wm_wdm2             ; 4 wait cycles on Data M.
Wm_dmwc5 := (Wm_wdm2|Wm_wdm0)   ; 5 wait cycles on Data M.
Wm_dmwc6 := (Wm_wdm2|Wm_wdm1)   ; 6 wait cycles on Data M.
Wm_dmwc7 := (Wm_wdm2|Wm_wdm1|Wm_wdm0) ; 7 wait cycles on Data M.

Wm_pmwc1 :=  Wm_wpm0            ; 1 wait cycle  on Prog M.
Wm_pmwc2 :=  Wm_wpm1            ; 2 wait cycles on Prog M.
Wm_pmwc3 := (Wm_wpm1|Wm_wpm0 )  ; 3 wait cycles on Prog M.
Wm_pmwc4 :=  Wm_wpm2            ; 4 wait cycles on Prog M.
Wm_pmwc5 := (Wm_wpm2|Wm_wpm0 )  ; 5 wait cycles on Prog M.
Wm_pmwc6 := (Wm_wpm2|Wm_wpm1 )  ; 6 wait cycles on Prog M.
Wm_pmwc7 := (Wm_wpm2|Wm_wpm1|Wm_wpm0) ; 7 wait cycles on Prog M.

;*************************
;* SPI Control Registers *
;*************************

SPI_PG	:= 0                    ; SPI register page

SPIDR	:= R253                 ; SPI Data register
spidr	 = r13

SPICR	:= R254                 ; SPI Control register
spicr	 = r14
.defstr SP_spen "spicr.7"	; Serial Peripheral Enable.
.defstr SP_bms  "spicr.6"	; SBUS/I2C bus Mode Selector.
.defstr SP_arb  "spicr.5"	; Arbitration flag bit.
.defstr SP_busy "spicr.4"	; SPI busy flag.
.defstr SP_cpol "spicr.3"	; SPI transmission clock polarity
.defstr SP_cpha "spicr.2"	; SPI transmission clock phase
.defstr SP_spr1 "spicr.1"	; SPI rate bit 1
.defstr SP_spr0 "spicr.0"	; SPI rate bit 0
SPm_spen    := ( 1 <- 7 )       ; Serial Peripheral Enable mask
SPm_bms     := ( 1 <- 6 )       ; SBUS/I2C bus selector mask
SPm_arb     := ( 1 <- 5 )       ; Arbitration mask
SPm_sp_busy := ( 1 <- 4 )       ; SPI busy mask
SPm_cpol    := ( 1 <- 3 )       ; SPI transmission clock polarity mask
SPm_cpha    := ( 1 <- 2 )       ; SPI transmission clock phase

SPm_8       := 0                ; SPI clock divider   8 = 1500 kHz (12MHz)
SPm_16      := 1                ; SPI clock divider  16 =  750 kHz (12MHz)
SPm_128     := 2                ; SPI clock divider 128 = 93.75 kHz (12MHz)
SPm_256     := 3                ; SPI clock divider 256 = 46.87 kHz (12MHz)


;**********************
;* I/O Port Registers *
;**********************
; P0DR, P1DR, P2DR, P3DR are mapped 
; in the system registers if DPRREM=0 in EMR2 register.
; They are mapped in page 21 if DPRREM=1 in EMR2 register

P0C_PG  := 2                    ; Port 0 control registers page
P0D_PG  := 21                   ; Port 0 data register page

P0DR    := R224                 ; Port 0 data register
P0DR_P  := R240                 ; Port 0 data register
P0C0R   := R240                 ; Port 0 control register 0
P0C1R   := R241                 ; Port 0 control register 1
P0C2R   := R242                 ; Port 0 control register 2
p0dr     = r0
p0dr_p   = r0
p0c0r    = r0
p0c1r    = r1
p0c2r    = r2

P1C_PG  := 2                    ; Port 1 control registers page
P1D_PG  := 21                   ; Port 1 data register page

P1DR    := R225                 ; Port 1 data register
P1DR_P  := R241                 ; Port 1 data register
P1C0R   := R244                 ; Port 1 control register 0
P1C1R   := R245                 ; Port 1 control register 1
P1C2R   := R246                 ; Port 1 control register 2
p1dr     = r1
p1dr_p   = r1
p1c0r    = r4
p1c1r    = r5
p1c2r    = r6

P2C_PG  := 2                    ; Port 2 control registers page
P2D_PG  := 21                   ; Port 2 data register page

P2DR    := R226                 ; Port 2 data register
P2DR_P  := R242                 ; Port 2 data register
P2C0R   := R248                 ; Port 2 control register 0
P2C1R   := R249                 ; Port 2 control register 1
P2C2R   := R250                 ; Port 2 control register 2
p2dr     = r2
p2dr_p   = r2
p2c0r    = r8
p2c1r    = r9
p2c2r    = r10

P3C_PG  := 2                    ; Port 3 control registers page
P3D_PG  := 21                   ; Port 3 data register page

P3DR    := R227                 ; Port 3 data register
P3DR_P  := R243                 ; Port 3 data register
P3C0R   := R252                 ; Port 3 control register 0
P3C1R   := R253                 ; Port 3 control register 1
P3C2R   := R254                 ; Port 3 control register 2
p3dr     = r3
p3dr_p   = r3
p3c0r    = r12
p3c1r    = r13
p3c2r    = r14

P4C_PG  := 3                    ; Port 4 control registers page

P4DR    := R228                 ; Port 4 data register
P4C0R   := R240                 ; Port 4 control register 0
P4C1R   := R241                 ; Port 4 control register 1
P4C2R   := R242                 ; Port 4 control register 2
p4dr     = r4
p4c0r    = r0
p4c1r    = r1
p4c2r    = r2

P5C_PG  := 3                    ; Port 5 control registers page

P5DR    := R229                 ; Port 5 data register
P5C0R   := R244                 ; Port 5 control register 0
P5C1R   := R245                 ; Port 5 control register 1
P5C2R   := R246                 ; Port 5 control register 2
p5dr     = r5
p5c0r    = r4
p5c1r    = r5
p5c2r    = r6

P6C_PG  := 3                    ; Port 6 control registers page
P6D_PG  := 3                    ; Port 6 data register page

P6DR    := R251                 ; Port 6 data register
P6C0R   := R248                 ; Port 6 control register 0
P6C1R   := R249                 ; Port 6 control register 1
P6C2R   := R250                 ; Port 6 control register 2
p6dr     = r11
p6c0r    = r8
p6c1r    = r9
p6c2r    = r10

P7C_PG  := 3                    ; Port 7 control registers page
P7D_PG  := 3                    ; Port 7 data register page

P7DR    := R255                 ; Port 7 data register
P7C0R   := R252                 ; Port 7 control register 0
P7C1R   := R253                 ; Port 7 control register 1
P7C2R   := R254                 ; Port 7 control register 2
p7dr     = r15
p7c0r    = r12
p7c1r    = r13
p7c2r    = r14

P8C_PG  := 43                   ; Port 8 control registers page
P8D_PG  := 43                   ; Port 8 data register page

P8DR    := R251                 ; Port 8 data register
P8C0R   := R248                 ; Port 8 control register 0
P8C1R   := R249                 ; Port 8 control register 1
P8C2R   := R250                 ; Port 8 control register 2
p8dr     = r11
p8c0r    = r8
p8c1r    = r9
p8c2r    = r10

P9C_PG  := 43                   ; Port 9 control registers page
P9D_PG  := 43                   ; Port 9 data register page

P9DR    := R255                 ; Port 9 data register
P9C0R   := R252                 ; Port 9 control register 0
P9C1R   := R253                 ; Port 9 control register 1
P9C2R   := R254                 ; Port 9 control register 2
p9dr     = r15
p9c0r    = r12
p9c1r    = r13
p9c2r    = r14

HDCTL2R := R251                 ; Port 2 handshake DMA control register
HDCTL3R := R255                 ; Port 3 handshake DMA control register
HDCTL4R := R243                 ; Port 4 handshake DMA control register
HDCTL5R := R247                 ; Port 5 handshake DMA control register
hdctl2r  = r11
hdctl3r  = r15
hdctl4r  = r3
hdctl5r  = r7

;Handshake DMA control register configuration.

HDm_hsdis := 0E0h               ; Handshake disabled mask
HDm_hso2  := 0C0h               ; Handshake output 2 lines mask
HDm_hso1  := 040h               ; Handshake output 1 line mask
HDm_hsi2  := 0A0h               ; Handshake input 2 lines mask
HDm_hsi1  := 020h               ; Handshake input 1 line mask
HDm_hsb   := 000h               ; Handshake bidirectional mask
HDm_den   := 000h               ; DMA enable mask
HDm_ddi   := 010h               ; DMA disable mask
HDm_ddw   := 000h               ; Data direction output mask (write)
HDm_ddr   := 008h               ; Data direction input mask (read)
HDm_dst   := 004h               ; DMA strobe on chip event mask
HDm_dcp0  := 000h               ; DMA channel capture0 mask
HDm_dcm0  := 002h               ; DMA channel compare0 mask

;**********************************
;* Multi Function Timer Registers *
;**********************************

T0D_PG  := 10                   ; MFTimer 0 data registers page
T0C_PG  := 9                    ; MFTimer 0 control registers page
T1D_PG  := 8                    ; MFTimer 1 data registers page
T1C_PG  := 9                    ; MFTimer 1 control registers page
T2D_PG  := 14                   ; MFTimer 2 data registers page
T2C_PG  := 13                   ; MFTimer 2 control registers page
T3D_PG  := 12                   ; MFTimer 3 data registers page
T3C_PG  := 13                   ; MFTimer 3 control registers page

T_REG0R	:= RR240                ; MFTimer REG0 load and capture register.
t_reg0r  = rr0
T_REG0HR := R240                ; Register 0 high register
t_reg0hr  = r0
T_REG0LR := R241                ; Register 0 low register
t_reg0lr  = r1

T_REG1R := RR242                ; MFTimer REG1 load constant 
t_reg1r  = rr2                  ; and capture register.
T_REG1HR := R242                ; Register 1 high register
t_reg1hr  = r2
T_REG1LR := R243                ; Register 1 low register
t_reg1lr  = r3

T_CMP0R := RR244                ; MFTimer CMP0 store compare constant.
t_cmp0r  = rr4