copy of st92163.inc

用ST92163开发的鼠标

;*****************************************************************************
;*           (c) ST MICROELECTRONICS - All Right Reserved                    *
;*****************************************************************************
;* THE SOFTWARE INCLUDED IN THIS FILE IS FOR GUIDANCE ONLY.                  *
;* ST MICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR  *
;* CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM USE OF THIS *
;* SOFTWARE.                                                                 *
;*===========================================================================*
;*      FILE            :  st90158.inc                                       *
;*      AUTHOR(s)       :  C Baek / Kh Choi of ST-Korea                      *
;*      DATE            :  08/01/99                                          *
;*      PROCESSOR       :  ST90158                                           *
;*      COMPILER        :  GNU C Compiler - V4.3                             *
;*                                                                           *
;*      DESCRIPTION     :  Include file for the definitions                  *
;*			   Registers and Bits of ST90158 family              *
;****************************************************************************/

.nlist

;***********************************
;* REGISTER FILE GROUPS DEFINITION *
;***********************************

BK00	:= 0			; r0 to r7  in group 0
BK01	:= 1			; r8 to r15 in group 0
BK10	:= 2			; r0 to r7  in group 1
BK11	:= 3			; r8 to r15 in group 1
BK20	:= 4			; r0 to r7  in group 2
BK21	:= 5			; r8 to r15 in group 2
BK30	:= 6			; r0 to r7  in group 3
BK31	:= 7			; r8 to r15 in group 3
BK40	:= 8			; r0 to r7  in group 4
BK41	:= 9			; r8 to r15 in group 4
BK50	:= 10			; r0 to r7  in group 5
BK51	:= 11			; r8 to r15 in group 5
BK60	:= 12			; r0 to r7  in group 6
BK61	:= 13			; r8 to r15 in group 6
BK70	:= 14			; r0 to r7  in group 7
BK71	:= 15			; r8 to r15 in group 7
BK80	:= 16			; r0 to r7  in group 8
BK81	:= 17			; r8 to r15 in group 8
BK90	:= 18			; r0 to r7  in group 9
BK91	:= 19			; r8 to r15 in group 9
BKA0	:= 20			; r0 to r7  in group A
BKA1	:= 21			; r8 to r15 in group A
BKB0	:= 22			; r0 to r7  in group B
BKB1	:= 23			; r8 to r15 in group B
BKC0	:= 24			; r0 to r7  in group C
BKC1	:= 25			; r8 to r15 in group C
BKD0	:= 26			; r0 to r7  in group D
BKD1	:= 27			; r8 to r15 in group D
BKE0	:= 28			; r0 to r7  in group E
BKE1	:= 29			; r8 to r15 in group E
BKF0	:= 30			; r0 to r7  in group F
BKF1	:= 31			; r8 to r15 in group F

BK_SYS	:= BKE0			; Group system definition
BK_F	:= BKF0			; page register definition

;********************
;* SYSTEM REGISTERS *
;********************

FCW	:= RR230		; Flags and control word.
fcw	 = rr6

CICR	:= R230			; Central interrupt control register.
cicr	 = r6
.defstr gcen "cicr.7"		; Global counter enable.
.defstr tlip "cicr.6"		; Top level interrupt pending bit
.defstr tli  "cicr.5"		; Top level interrupt bit.
.defstr ien  "cicr.4"		; Interrupt enable flag.
.defstr iam  "cicr.3"		; Interrupt arbitration mode.
.defstr cpl2 "cicr.2"		; Current priority level bit 2.
.defstr cpl1 "cicr.1"		; Current priority level bit 1.
.defstr cpl0 "cicr.0"		; Current priority level bit 0.
Im_gcenm := ( 1 <- 7 )          ; Global counter enable bit mask
Im_tlipm := ( 1 <- 6 )          ; Top level interrupt pending mask.
Im_tlim	 := ( 1 <- 5 )          ; Top level interrupt mask.
Im_ienm  := ( 1 <- 4 )          ; Interrupt enable flag mask.
Im_iamm  := ( 1 <- 3 )          ; Interrupt arbitration mode mask.
Im_cpl2m := ( 1 <- 2 )          ; Current priority level bit 2 mask.
Im_cpl1m := ( 1 <- 1 )          ; Current priority level bit 1 mask.
Im_cpl0m := ( 1 <- 0 )          ; Current priority level bit 0 mask.
Im_cplm  := (Im_cpl2m|Im_cpl1m|Im_cpl0m ) ; Current priority level

FLAGR	:= R231			; Flags register.
flagr	 = r7
.defstr c   "flagr.7"		; Carry flag.
.defstr z   "flagr.6"		; Zero flag.
.defstr s   "flagr.5"		; Sign flag.
.defstr v   "flagr.4"		; Overflow flag.
.defstr d   "flagr.3"		; Decimal adjust flag.
.defstr h   "flagr.2"		; Half carry flag.
.defstr uf  "flagr.1"		; User flag 1.
.defstr dp  "flagr.0"		; Data/program memory flag.
FLm_cm	:= ( 1 <- 7 )		; Carry flag mask.
FLm_zm  := ( 1 <- 6 )		; Zero flag mask.
FLm_sm  := ( 1 <- 5 )		; Sign flag mask.
FLm_vm  := ( 1 <- 4 )		; Overflow flag mask.
FLm_dm  := ( 1 <- 3 )		; Decimal adjust flag mask.
FLm_hm  := ( 1 <- 2 )		; Half carry flag mask.
FLm_ufm := ( 1 <- 1 )		; User flag 1 mask.
FLm_dpm := ( 1 <- 0 )		; Data/program memory mask.

RPP	:= RR232		; Register pointer pair.
rpp	 = rr8

RP0R	:= R232			; Register pointer # 0.
rp0r	 = r8
.defstr rp0s "rp0r.2"		; Register pointer selector
RPm_rp0sm := ( 1 <- 2 )         ; Register pointer selector mask

RP1R	:= R233                 ; Register pointer # 1.
rp1r	 = r9
.defstr rp1s "rp1r.2"		; Register pointer selector
RPm_rp1sm := ( 1 <- 2 )         ; Register pointer selector mask

PPR	:= R234			; Page pointer register.
ppr	 = r10

MODER	:= R235			; Mode register.
moder    = r11
.defstr ssp   "moder.7"		; System stack pointer flag (Int/Ext).
.defstr usp   "moder.6"		; User stack pointer flag (Int/Ext).
.defstr div2  "moder.5"		; External clock divided by 2.
.defstr prs2  "moder.4"		; Internal clock prescaling bit 2.
.defstr prs1  "moder.3"		; Internal clock prescaling bit 1.
.defstr prs0  "moder.2"		; Internal clock prescaling bit 0.
.defstr brqen "moder.1"		; Bus request enable.
.defstr himp  "moder.0"		; High impedance enable.
MOm_sspm := ( 1 <- 7 )          ; System stack pointer mask (Int/Ext).
MOm_uspm := ( 1 <- 6 )          ; User stack pointer mask (Int/Ext).
MOm_div2m := ( 1 <- 5 )         ; External clock divided by 2 mask.
MOm_prs2m := ( 1 <- 4 )         ; Internal clock prescaling bit 2 mask.
MOm_prs1m := ( 1 <- 3 )         ; Internal clock prescaling bit 1 mask.
MOm_prs0m := ( 1 <- 2 )         ; Internal clock prescaling bit 0 mask.
MOm_prsm := (MOm_prs2m|MOm_prs1m|MOm_prs0m) ; Internal clock prescaler
MOm_brqenm := ( 1 <- 1 )        ; Bus request enable mask.
MOm_himpm := ( 1 <- 0 )         ; High impedence enable mask.

USPR	:= RR236		; User stack pointer.
uspr	 = rr12
USPHR	:= R236			; User stack pointer, msb.
usphr	 = r12
USPLR	:= R237			; User stack pointer, lsb.
usplr    = r13
SSPR	:= RR238		; System stack pointer.
sspr	 = rr14
SSPHR	:= R238			; System stack pointer, msb.
ssphr	 = r14
SSPLR	:= R239			; System stack pointer, lsb.
ssplr	 = r15

;***************************************
;* External Interrupt Control Register *
;***************************************

EXINT_PG := 0			; EXTERNAL interrupt register page

EITR	:= R242			; External interrupt trigger level register
eitr	 = r2
.defstr tea0 "eitr.0"		; Trigger Event A0 bit
.defstr tea1 "eitr.1"		; Trigger Event A1 bit
.defstr teb0 "eitr.2"		; Trigger Event B0 bit
.defstr teb1 "eitr.3"		; Trigger Event B1 bit
.defstr tec0 "eitr.4"		; Trigger Event C0 bit
.defstr tec1 "eitr.5"		; Trigger Event C1 bit
.defstr ted0 "eitr.6"		; Trigger Event D0 bit
.defstr ted1 "eitr.7"		; Trigger Event D1 bit
EIm_tea0m := ( 1 <- 0 )		; Trigger Event A0 mask
EIm_tea1m := ( 1 <- 1 )		; Trigger Event A1 mask
EIm_teb0m := ( 1 <- 2 )		; Trigger Event B0 mask
EIm_teb1m := ( 1 <- 3 )		; Trigger Event B1 mask
EIm_tec0m := ( 1 <- 4 )		; Trigger Event C0 mask
EIm_tec1m := ( 1 <- 5 )		; Trigger Event C1 mask
EIm_ted0m := ( 1 <- 6 )		; Trigger Event D0 mask
EIm_ted1m := ( 1 <- 7 )		; Trigger Event D1 mask

EIPR	:= R243			; External interrupt pending register
eipr	 = r3
.defstr ipa0 "eipr.0"		; Interrupt Pending bit Channel A0
.defstr ipa1 "eipr.1"		; Interrupt Pending bit     "   A1
.defstr ipb0 "eipr.2"		; Interrupt Pending bit     "   B0
.defstr ipb1 "eipr.3"		; Interrupt Pending bit     "   B1
.defstr ipc0 "eipr.4"		; Interrupt Pending bit     "   C0
.defstr ipc1 "eipr.5"		; Interrupt Pending bit     "   C1
.defstr ipd0 "eipr.6"		; Interrupt Pending bit     "   D0
.defstr ipd1 "eipr.7"		; Interrupt Pending bit     "   D1
EIm_ipa0m := ( 1 <- 0 )		; Interrupt Pending A0 mask
EIm_ipa1m := ( 1 <- 1 )		; Interrupt Pending A1 mask
EIm_ipb0m := ( 1 <- 2 )		; Interrupt Pending B0 mask
EIm_ipb1m := ( 1 <- 3 )		; Interrupt Pending B1 mask
EIm_ipc0m := ( 1 <- 4 )		; Interrupt Pending C0 mask
EIm_ipc1m := ( 1 <- 5 )		; Interrupt Pending C1 mask
EIm_ipd0m := ( 1 <- 6 )		; Interrupt Pending D0 mask
EIm_ipd1m := ( 1 <- 7 )		; Interrupt Pending D1 mask

EIMR	:= R244			; External interrupt mask register
eimr	 = r4
.defstr ima0 "eimr.0"		; Int. A0 bit
.defstr ima1 "eimr.1"		; Int. A1 bit
.defstr imb0 "eimr.2"		; Int. B0 bit
.defstr imb1 "eimr.3"		; Int. B1 bit
.defstr imc0 "eimr.4"		; Int. C0 bit
.defstr imc1 "eimr.5"		; Int. C1 bit
.defstr imd0 "eimr.6"		; Int. D0 bit
.defstr imd1 "eimr.7"		; Int. D1 bit
EIm_ia0m := ( 1 <- 0 )		; Int. A0 mask
EIm_ia1m := ( 1 <- 1 )		; Int. A1 mask
EIm_ib0m := ( 1 <- 2 )		; Int. B0 mask
EIm_ib1m := ( 1 <- 3 )		; Int. B1 mask
EIm_ic0m := ( 1 <- 4 )		; Int. C0 mask
EIm_ic1m := ( 1 <- 5 )		; Int. C1 mask
EIm_id0m := ( 1 <- 6 )		; Int. D0 mask
EIm_id1m := ( 1 <- 7 )		; Int. D1 mask

EIPLR	:= R245			; Ext. interrupt priority level register
eiplr	 = r5
.defstr pla0 "eiplr.0"		; Priority Level channel A0 bit
.defstr pla1 "eiplr.1"		; Priority Level channel A1 bit
.defstr plb0 "eiplr.2"		; Priority Level channel B0 bit
.defstr plb1 "eiplr.3"		; Priority Level channel B1 bit
.defstr plc0 "eiplr.4"		; Priority Level channel C0 bit
.defstr plc1 "eiplr.5"		; Priority Level channel C1 bit
.defstr pld0 "eiplr.6"		; Priority Level channel D0 bit
.defstr pld1 "eiplr.7"		; Priority Level channel D1 bit
EIm_plam := ( 3 <- 0 )		; Priority Level group A0,A1
EIm_plbm := ( 3 <- 2 )		; Priority Level group B0,B1
EIm_plcm := ( 3 <- 4 )		; Priority Level group C0,C1
EIm_pldm := ( 3 <- 6 )		; Priority Level group D0,D1

EIVR	:= R246			; External interrupt vector register
eivr	 = r6
.defstr ewen  "eivr.0"		; External wait enable
.defstr ia0s  "eivr.1"		; Interrupt A0 selection
.defstr tlis  "eivr.2"		; Top level input selection
.defstr tltev "eivr.3"		; Top level trigger event
EIm_ewenm := ( 1 <- 0 )		; External wait enable mask
EIm_iaosm := ( 1 <- 1 )		; Interrupt A0 selection mask
EIm_tlism := ( 1 <- 2 )		; Top level Input selection mask
EIm_tltevm := ( 1 <- 3 )	; Top level trigger event mask

NICR	:= R247			; Nested interrupt control register
nicr	 = r7
.defstr tlnm "nicr.7"		; Top level not maskable
EIm_tlnmm := ( 1 <- 7 )		; Top level not maskable mask

;************************************
;* Timer Watchdog Control Registers *
;************************************

WDT_PG	:= 0			; Timer Watchdog page

WDTR	:= RR248		; TWD timer constant register.
wdtr	 = rr8
WDTHR	:= R248			; TWD timer high constant register
wdthr	 = r8
WDTLR	:= R249			; TWD timer low constant register
wdtlr	 = r9
WDTPR	:= R250			; TWD timer prescaler constant register
wdtpr	 = r10

WDTCR	:= R251			; TWD timer control register
wdtcr	 = r11
.defstr WD_stsp  "wdtcr.7"	; TWD start stop.
.defstr WD_sc    "wdtcr.6"	; TWD single continuous mode.
.defstr WD_inmd1 "wdtcr.5"	; Input mode 1
.defstr WD_inmd2 "wdtcr.4"	; Input mode 2
.defstr WD_inen  "wdtcr.3"	; TWD input section enable/disable.
.defstr WD_outmd "wdtcr.2"	; TWD output mode.
.defstr WD_wrout "wdtcr.1"	; TWD output bit.
.defstr WD_outen "wdtcr.0"	; TWD output enable.
WDm_stsp    := ( 1 <- 7 )       ; TWD start stop mask
WDm_sc      := ( 1 <- 6 )       ; TWD single continuous mode mask
WDm_inen    := ( 1 <- 3 )       ; TWD input section enable/disable mask
WDm_outmd   := ( 1 <- 2 )       ; TWD output mode mask
WDm_wrout   := ( 1 <- 1 )       ; TWD output bit mask
WDm_outen   := ( 1 <- 0 )       ; TWD output enable mask

WDm_inm_evc := 0                ; TWD input mode event counter.
WDm_inm_g   := 010h             ; TWD input mode gated.