st92163.inc

用ST92163开发的鼠标

s_rdapr  = r1                   ; receive DMA address pointer register
.equiv S_TDCPR , R242                 ; transmit DMA counter pointer register
s_tdcpr  = r2                   ; transmit DMA counter pointer register
.equiv S_TDAPR , R243                 ; transmit DMA address pointer register
s_tdapr  = r3                   ; transmit DMA address pointer register

.equiv S_IVR   , R244                 ; interrupt vector register
s_ivr    = r4                   ; interrupt vector register

.equiv S_ACR   , R245                 ; address compare register
s_acr    = r5                   ; address compare register

.equiv S_IMR   , R246                 ; interrupt mask register
s_imr    = r6                   ; interrupt mask register
#define S_txdi  s_imr.0	; transmitter data interrupt
#define S_rxdi  s_imr.1	; receiver data interrupt
#define S_rxb   s_imr.2	; receiver break
#define S_rxa   s_imr.3	; receiver address
#define S_rxe   s_imr.4	; receiver error
#define S_txeob s_imr.5	; transmit end of block
#define S_rxeob s_imr.6	; receive end of block
#define S_bsn   s_imr.7	; Buffer or shift register empty.
.equiv Sm_txdi  , ( 1 <- 0 )		; transmitter data interrupt mask
.equiv Sm_rxdi  , ( 1 <- 1 )		; receiver data interrupt mask
.equiv Sm_rxb   , ( 1 <- 2 )		; receiver break mask
.equiv Sm_rxa   , ( 1 <- 3 )		; receiver address mask
.equiv Sm_rxe   , ( 1 <- 4 )		; receiver error mask
.equiv Sm_txeob , ( 1 <- 5 )		; transmit end of block mask
.equiv Sm_rxeob , ( 1 <- 6 )		; receive end of block mask
.equiv Sm_bsn   , ( 1 <- 7 )		; Buffer or shift register empty mask.

.equiv S_ISR   , R247                 ; interrupt status register
s_isr    = r7                   ; interrupt status register
#define S_txsem s_isr.0	; transmit shift register empty
#define S_txbem s_isr.1	; transmit buffer register empty
#define S_rxdp  s_isr.2	; received data pending bit
#define S_rxbp  s_isr.3	; received break pending bit
#define S_rxap  s_isr.4	; received address pending bit
#define S_pe    s_isr.5	; parity error pending bit
#define S_fe    s_isr.6	; framing error pending bit
#define S_oe    s_isr.7	; overrun error pending bit
.equiv Sm_txsem , ( 1 <- 0 )		; transmit shift register empty mask
.equiv Sm_txbem , ( 1 <- 1 )		; transmit buffer register empty mask
.equiv Sm_rxdp  , ( 1 <- 2 )		; received data pending mask
.equiv Sm_rxbp  , ( 1 <- 3 )		; received break pending mask
.equiv Sm_rxap  , ( 1 <- 4 )		; received address pending mask
.equiv Sm_pe    , ( 1 <- 5 )		; parity error pending mask
.equiv Sm_fe    , ( 1 <- 6 )		; framing error pending mask
.equiv Sm_oe    , ( 1 <- 7 )		; overrun error pending mask

.equiv S_RXBR  , R248                 ; receive buffer register
s_rxbr   = r8                   ; receive buffer register

.equiv S_TXBR  , R248                 ; transmit buffer register
s_txbr   = r8                   ; transmit buffer register

.equiv S_IDPR  , R249                 ; interrupt/DMA priority register
s_idpr   = r9                   ; interrupt/DMA priority register
#define S_txd  s_idpr.3	; transmitter DMA
#define S_rxd  s_idpr.4	; receiver DMA
#define S_sa   s_idpr.5	; set address
#define S_sb   s_idpr.6	; set break
#define S_amen s_idpr.7	; address mode enable
.equiv Sm_pri  , 07h			; interrupt/DMA priority mask
.equiv Sm_txd  , ( 1 <- 3 )		; transmitter DMA mask
.equiv Sm_rxd  , ( 1 <- 4 )		; receiver DMA mask
.equiv Sm_sa   , ( 1 <- 5 )		; set address mask
.equiv Sm_sb   , ( 1 <- 6 )		; set break mask
.equiv Sm_amen , ( 1 <- 7 )		; address mode enable mask

.equiv S_CHCR  , R250                 ; Character configuration register
s_chcr   = r10                  ; Character configuration register
#define S_ab   s_chcr.4	; Address/9th bit
#define S_pen  s_chcr.5	; Parity enable
#define S_ep   s_chcr.6	; Even parity
#define S_am   s_chcr.7	; Address mode
  
.equiv Sm_wl5  , 000h			; 5 bits data word mask
.equiv Sm_wl6  , 001h			; 6 bits data word mask
.equiv Sm_wl7  , 002h			; 7 bits data word mask
.equiv Sm_wl8  , 003h			; 8 bits data word mask

.equiv Sm_sb10 , 000h			; 1.0 stop bit mask
.equiv Sm_sb15 , 004h			; 1.5 stop bit mask
.equiv Sm_sb20 , 008h			; 2.0 stop bit mask
.equiv Sm_sb25 , 00Ch			; 2.5 stop bit mask

.equiv Sm_ab   , 010h			; address bit insertion mask
.equiv Sm_pen  , 020h			; parity enable mask
.equiv Sm_ep   , 040h			; Even parity mask
.equiv Sm_oddp , 000h			; odd parity mask
.equiv Sm_am   , 080h			; address mode mask

.equiv S_CCR   , R251                 ; Clock configuration register
s_ccr    = r11                  ; Clock configuration register
#define S_stpen s_ccr.0	; stick parity enable
#define S_lben  s_ccr.1	; loop back enable
#define S_aen   s_ccr.2	; auto echo enable
#define S_cd    s_ccr.3	; Clock divider
#define S_xbrg  s_ccr.4	; External baud rate generator source
#define S_xrx   s_ccr.5	; External receiver source
#define S_oclk  s_ccr.6	; output clock selection
#define S_xtclk s_ccr.7	; transmit clock selection
.equiv Sm_stpen , ( 1 <- 0 )          ; stick parity enable mask
.equiv Sm_lben  , ( 1 <- 1 )          ; loop back enable mask
.equiv Sm_aen   , ( 1 <- 2 )          ; auto echo enable mask
.equiv Sm_cd    , ( 1 <- 3 )          ; Clock divider mask
.equiv Sm_xbrg  , ( 1 <- 4 )          ; External baud rate generator source mask
.equiv Sm_xrx   , ( 1 <- 5 )          ; External receiver source mask
.equiv Sm_oclk  , ( 1 <- 6 )          ; output clock selection mask
.equiv Sm_xtclk , ( 1 <- 7 )          ; transmit clock selection mask

.equiv S_BRGR  , RR252                ; baud rate generator register
s_brgr   = rr12                 ; baud rate generator register
.equiv S_BRGHR , R252                 ; baud rate generator reg. high
s_brghr  = r12                  ; baud rate generator reg. high
.equiv S_BRGLR , R253                 ; baud rate generator reg. low
s_brglr  = r13                  ; baud rate generator reg. low

.equiv S_SICR  , R254                 ; Synchronous input control register
s_sicr   = r14                  ; Synchronous input control register
#define S_inpen s_sicr.2      ; All input disable
#define S_dcdpl s_sicr.3      ; DCD input polarity
#define S_dcden s_sicr.4      ; DCD input enable
#define S_xckpl s_sicr.5      ; Receiver clock polarity
#define S_inpl  s_sicr.6      ; SIN input polarity
#define S_smen  s_sicr.7      ; Synchronous mode enable
.equiv Sm_inpen , ( 1 <- 2 )          ; All input disable mask
.equiv Sm_dcdpl , ( 1 <- 3 )          ; DCD input polarity mask
.equiv Sm_dcden , ( 1 <- 4 )          ; DCD input enable mask
.equiv Sm_xckpl , ( 1 <- 5 )          ; Receiver clock polarity mask
.equiv Sm_inpl  , ( 1 <- 6 )          ; SIN input polarity mask
.equiv Sm_smen  , ( 1 <- 7 )          ; Synchronous mode enable mask

.equiv S_SOCR  , R255                 ; Synchronous output control register
s_socr   = r15                  ; Synchronous output control register
#define S_ctspl s_socr.2      ; CTS output polarity 
#define S_ctsen s_socr.3      ; CTS output enable
#define S_ocksb s_socr.4      ; Transmitter clock stand-by level
#define S_ockpl s_socr.5      ; Transmitter clock polarity
#define S_outsb s_socr.6      ; SOUT output stand-by level
#define S_outpl s_socr.7      ; SOUT output polarity
.equiv Sm_ctspl , ( 1 <- 2 )          ; CTS output polarity mask
.equiv Sm_ctsen , ( 1 <- 3 )          ; CTS output enable mask
.equiv Sm_ocksb , ( 1 <- 4 )          ; Transmitter clock stand-by level mask
.equiv Sm_ockpl , ( 1 <- 5 )          ; Transmitter clock polarity mask
.equiv Sm_outsb , ( 1 <- 6 )          ; SOUT output stand-by level mask
.equiv Sm_outpl , ( 1 <- 7 )          ; SOUT output polarity mask

.equiv MIRROR_PG , 60                 ; Mirrir control registers page
.equiv MIRRA   , R246                 ; mirror register 
.equiv MIRRB   , R247                 ; mirror register 

;*************************
;* MMU Control Registers *
;*************************
; MMU data page registers located in 
; System Group E (bit DPRREM=1 in EMR2 register)

.equiv DPR0	, R224
.equiv dpr0	, r0
.equiv DPR1	, R225
.equiv dpr1	, r1
.equiv DPR2	, R226
.equiv dpr2	, r2
.equiv DPR3	, R227
.equiv dpr3	, r3

; MMU data page registers located in 
; the page 21 (bit DPRREM=0 in EMR2 register)

.equiv MMU_PG	, 21

.equiv DPR0_P	, R240
dpr0_p   = r0
.equiv DPR1_P	, R241
dpr1_p   = r1
.equiv DPR2_P	, R242
dpr2_p   = r3
.equiv DPR3_P	, R243
dpr3_p   = r4

.equiv CSR	, R244			; MMU code segment register
csr      = r4
.equiv ISR	, R248			; MMU interrupt segment register
isr      = r8
.equiv DMASR	, R249			; MMU DMA segment register
dmasr    = r6

.equiv EMR1	, R245			; MMU configuration registers
emr1     = r5
#define mc       emr1.6       ; mode control
#define ds2n     emr1.5       ; data strobe 2 enable
#define asaf     emr1.4       ; address strobe as alternate function
#define nmb      emr1.3       ; no multiplexed bus
#define eto      emr1.2       ; external toggle
#define bsz      emr1.1       ; bus size
#define romless  emr1.0       ; romless
.equiv EMR1_mc      , ( 1 <- 6 )      ; mode control
.equiv EMR1_ds2n    , ( 1 <- 5 )      ; data strobe 2 enable
.equiv EMR1_asaf    , ( 1 <- 4 )      ; address strobe as alternate function
.equiv EMR1_nmb     , ( 1 <- 3 )      ; no multiplexed bus
.equiv EMR1_eto     , ( 1 <- 2 )      ; external toggle
.equiv EMR1_bsz     , ( 1 <- 1 )      ; bus size
.equiv EMR1_romless , ( 1 <- 0 )      ; romless

.equiv EMR2	, R246
emr2     = r6
#define bromless emr2.7       ; Boot-Romless
#define encsr    emr2.6       ; ENable Code Segment register
#define dprrem   emr2.5       ; data Page register Remapped
#define memsel   emr2.4       ; MEMory SELect
#define las1     emr2.3       ; Lower memory Address strobe Stretch bit 1
#define las0     emr2.2       ; Lower memory Address strobe Stretch bit 0
#define uas1     emr2.1       ; Upper memory Address strobe Stretch bit 1
#define uas0     emr2.0       ; Upper memory Address strobe Stretch bit 0
.equiv EMR2_bromless , ( 1 <- 7 )     ; Boot-Romless
.equiv EMR2_encsr    , ( 1 <- 6 )     ; ENable Code Segment register
.equiv EMR2_dprrem   , ( 1 <- 5 )     ; data Page register Reapped
.equiv EMR2_memsel   , ( 1 <- 4 )     ; MEMory SELect
.equiv EMR2_las      , ( 3 <- 2 )     ; Lower memory Address strobe Stretch
.equiv EMR2_uas      , ( 3 <- 0 )     ; Upper memory Address strobe stretch

;**************************
;* RCCU Control Registers *
;**************************

.equiv RCCU_PG , 55                   ; RCCU registers page

.equiv CLKCTL	, R240                 ; Clock Control register 
clkctl   = r0                   ; Clock Control register 
#define lpowfi   clkctl.0     ; Low Power Mode during WFI bit
#define wficksel clkctl.1     ; WFI clock select bit
#define ckafsel  clkctl.2     ; Alternate Function Clock Select bit
#define sresen   clkctl.3     ; HALT command bit
#define intsel   clkctl.7     ; Interrupt selection bit
.equiv Cm_lpowfi   , ( 1 <- 0 )       ; Low Power Mode during Wait for interrupt
.equiv Cm_wficksel , ( 1 <- 1 )       ; WFI Clock select
.equiv Cm_ckafsel  , ( 1 <- 2 )       ; Alternate Function Clock Select
.equiv Cm_sresen   , ( 1 <- 3 )       ; HALT command  
.equiv Cm_intsel   , ( 1 <- 7 )       ; Interrupt selection 

.equiv CLK_FLAG , R242		; Clock Flag register 
clk_flag  = r2			; Clock Flag register 
#define csucksel clk_flag.0   ; System Clock Selection bit
#define lock     clk_flag.1   ; System Clock lock flag
#define ckafst   clk_flag.2   ; Flag for Alternate Function Clock bit
#define xtdiv16  clk_flag.3   ; CLOCK2/16 selection bit
#define xtstop   clk_flag.4   ; Xtal oscillator Stop bit
#define softres  clk_flag.5   ; Software Reset flag bit
#define wdgres   clk_flag.6   ; Watchdog Reset flag bit
#define exstp    clk_flag.7   ; External stop flag bit
.equiv Cm_csucksel , ( 1 <- 0 )       ; System Clock selection
.equiv Cm_lock     , ( 1 <- 1)        ; System Clock lock flag
.equiv Cm_ckafst   , ( 1 <- 2 )       ; Flag for alternate function clock
.equiv Cm_xtdiv16  , ( 1 <- 3 )       ; CLOCK2/16 selection
.equiv Cm_xtstop   , ( 1 <- 4 )       ; Xtal oscillator stop
.equiv Cm_softres  , ( 1 <- 5 )       ; Software reset flag
.equiv Cm_wdgres   , ( 1 <- 6 )       ; Watchdog reset flag
.equiv Cm_exstp    , ( 1 <- 7 )       ; external stop flag

.equiv PLLCONF , R246			; PLL configuration register 
.equiv pllconf , r6			; PLL configuration register 

.equiv Cm_mul14  , 020h               ; PLL multiplication factor : 14
.equiv Cm_mul10  , 000h               ; PLL multiplication factor : 10
.equiv Cm_mul8   , 030h               ; PLL multiplication factor : 8
.equiv Cm_mul6   , 010h               ; PLL multiplication factor : 6

.equiv Cm_div1   , 000h               ; PLL divider factor : 1
.equiv Cm_div2   , 001h               ; PLL divider factor : 2
.equiv Cm_div3   , 002h               ; PLL divider factor : 3
.equiv Cm_div4   , 003h               ; PLL divider factor : 4
.equiv Cm_div5   , 004h               ; PLL divider factor : 5
.equiv Cm_div6   , 005h               ; PLL divider factor : 6
.equiv Cm_div7   , 006h               ; PLL divider factor : 7
.equiv Cm_plloff , 007h               ; PLL OFF 

.list

;***************************** end of file **********************************/