st92163.inc

用ST92163开发的鼠标

.equiv T_CMP0HR , R244                ; Compare 0 high register
t_cmp0hr  = r4
.equiv T_CMP0LR , R245                ; Compare 0 low register
t_cmp0lr  = r5

.equiv T_CMP1R , RR246                ; MFTimer CMP1 store compare constant.
t_cmp1r  = rr6
.equiv T_CMP1HR , R246                ; Compare 1 high register
t_cmp1hr  = r6
.equiv T_CMP1LR , R247                ; Compare 1 low register
t_cmp1lr  = r7

.equiv T_TCR	, R248                 ; MFTimer Control Register.
t_tcr    = r8
#define T_cs    t_tcr.0	; Counter status
#define T_of0   t_tcr.1	; over/underflow on CAP on REG0
#define T_udcs  t_tcr.2	; up/down count status
#define T_udc   t_tcr.3	; up/down count
#define T_ccl   t_tcr.4	; Counter clear
#define T_ccmp0 t_tcr.5	; Clear on compare 0
#define T_ccp0  t_tcr.6	; Clear on capture
#define T_cen   t_tcr.7	; Counter enable        
.equiv Tm_cs    , ( 1 <- 0 )		; Counter status mask
.equiv Tm_of0   , ( 1 <- 1 )		; over/underflow mask on CAP on REG0
.equiv Tm_udcs  , ( 1 <- 2 )		; up/down count status mask
.equiv Tm_udc   , ( 1 <- 3 )		; up/down count mask
.equiv Tm_ccl   , ( 1 <- 4 )		; Counter clear mask
.equiv Tm_ccmp0 , ( 1 <- 5 )		; Clear on compare mask
.equiv Tm_ccp0  , ( 1 <- 6 )		; Clear on capture mask
.equiv Tm_cen   , ( 1 <- 7 )		; Counter enable mask

.equiv T_TMR   , R249                 ; MFTimer Mode Register.
t_tmr    = r9
#define T_co  t_tmr.0		; Continuous/one shot bit
#define T_ren t_tmr.1		; retrigger enable bit
#define T_eck t_tmr.2		; Enable clocking mode bit
#define T_rm0 t_tmr.3		; register 0 mode bit
#define T_rm1 t_tmr.4		; register 1 mode bit
#define T_bm  t_tmr.5		; bivalue mode bit
#define T_oe0 t_tmr.6		; output 0 enable bit
#define T_oe1 t_tmr.7		; output 1 enable bit
.equiv Tm_co   , ( 1 <- 0 )		; Continuous/one shot mask
.equiv Tm_ren  , ( 1 <- 1 )		; retrigger enable mask
.equiv Tm_eck  , ( 1 <- 2 )		; Enable clocking mode mask
.equiv Tm_rm0  , ( 1 <- 3 )		; register 0 mode mask
.equiv Tm_rm1  , ( 1 <- 4 )		; register 1 mode mask
.equiv Tm_bm   , ( 1 <- 5 )		; bivalue mode mask
.equiv Tm_oe0  , ( 1 <- 6 )		; output 0 enable mask
.equiv Tm_oe1  , ( 1 <- 7 )		; output 1 enable mask

.equiv T_ICR   , R250                 ; MFTimer External Input Control Register.
t_icr    = r10

.equiv Tm_exb_f   , 01h               ; External B falling edge sensitive mask
.equiv Tm_exb_r   , 02h               ; External B rising edge sensitive mask
.equiv Tm_exb_rf  , 03h               ; External B falling and rising edge mask
.equiv Tm_exa_f   , 04h               ; External A falling edge sensitive mask
.equiv Tm_exa_r   , 08h               ; External A rising edge sensitive mask
.equiv Tm_exa_rf  , 0Ch               ; External A falling and rising edge mask
.equiv Tm_ab_ii   , 00h               ; A I/O B I/O mask
.equiv Tm_ab_it   , 10h               ; A I/O B trigger mask
.equiv Tm_ab_gi   , 20h               ; A gate B I/O mask
.equiv Tm_ab_gt   , 30h               ; A gate B trigger mask
.equiv Tm_ab_ie   , 40h               ; A I/O B external clock mask
.equiv Tm_ab_ti   , 50h               ; A trigger B I/O mask
.equiv Tm_ab_ge   , 60h               ; A gate B external clock mask
.equiv Tm_ab_tt   , 70h               ; A trigger B trigger mask
.equiv Tm_ab_cucd , 80h               ; A clock up B clock down mask
.equiv Tm_ab_ue   , 90h               ; A clock up/down B external clock mask
.equiv Tm_ab_tutd , 0A0h              ; A trigger up B trigger down mask
.equiv Tm_ab_ui   , 0B0h              ; A up/down clock B I/O mask
.equiv Tm_ab_aa   , 0C0h              ; A autodiscr. B autodiscr. mask
.equiv Tm_ab_te   , 0D0h              ; A trigger B external clock mask
.equiv Tm_ab_et   , 0E0h              ; A external clock B trigger mask
.equiv Tm_ab_tg   , 0F0h              ; A trigger B gate mask

.equiv T_PRSR  , R251                 ; MFTimer prescaler register
t_prsr   = r11

.equiv T_OACR  , R252                 ; MFTimer Output A Control Register.
t_oacr   = r12
.equiv Tm_cev     , 02h		; on chip event bit on COMPARE 0 mask

.equiv T_OBCR  , R253                 ; MFTimer Output B Control Register.
t_obcr   = r13
.equiv Tm_op      , 01h               ; output preset bit mask
.equiv Tm_oev     , 02h               ; on chip event bit on OVF/UDF mask
.equiv Tm_ou_set  , 00h               ; overflow underflow set mask
.equiv Tm_ou_tog  , 04h               ; overflow underflow toggle mask
.equiv Tm_ou_res  , 08h               ; overflow underflow reset mask
.equiv Tm_ou_nop  , 0Ch               ; overflow underflow nop mask
.equiv Tm_c1_set  , 00h               ; Compare 1 set mask
.equiv Tm_c1_tog  , 10h               ; Compare 1 toggle mask
.equiv Tm_c1_res  , 20h               ; Compare 1 reset mask
.equiv Tm_c1_nop  , 30h               ; Compare 1 nop mask
.equiv Tm_c0_set  , 00h               ; Compare 0 set mask
.equiv Tm_c0_tog  , 40h               ; Compare 0 toggle mask
.equiv Tm_c0_res  , 80h               ; Compare 0 reset mask
.equiv Tm_c0_nop  , 0C0h              ; Compare 0 nop mask

.equiv T_FLAGR , R254                 ; MFTimer Flags Register.
t_flagr  = r14
#define T_ao   t_flagr.0	; and/or on capture interrupt
#define T_ocm0 t_flagr.1	; overrun compare 0
#define T_ocp0 t_flagr.2	; overrun capture 0
#define T_ouf  t_flagr.3	; overflow underflow flag
#define T_cm1  t_flagr.4	; successful compare 1
#define T_cm0  t_flagr.5	; successful compare 0
#define T_cp1  t_flagr.6	; successful capture 1 
#define T_cp0  t_flagr.7	; successful capture 0
.equiv Tm_ao   , ( 1 <- 0 )		; and/or on capture interrupt mask
.equiv Tm_ocm0 , ( 1 <- 1 )		; overrun compare 0 mask
.equiv Tm_ocp0 , ( 1 <- 2 )		; overrun capture 0 mask
.equiv Tm_ouf  , ( 1 <- 3 )		; overflow underflow flag mask
.equiv Tm_cm1  , ( 1 <- 4 )		; successful compare 1 mask
.equiv Tm_cm0  , ( 1 <- 5 )		; successful compare 0 mask
.equiv Tm_cp1  , ( 1 <- 6 )		; successful capture 1 mask
.equiv Tm_cp0  , ( 1 <- 7 )		; successful capture 0 mask

.equiv T_IDMR  , R255                 ; MFTimer Interrupt DMA Mask Register.
t_idmr   = r15
#define T_oui   t_idmr.0	; overflow underflow interrupt
#define T_cm1i  t_idmr.1	; Compare 1 interrupt
#define T_cm0i  t_idmr.2	; Compare 0 interrupt
#define T_cm0d  t_idmr.3	; Compare 0 DMA
#define T_cp1i  t_idmr.4	; Capture 1 interrupt
#define T_cp0i  t_idmr.5	; Capture 0 interrupt
#define T_cp0d  t_idmr.6	; Capture 0 DMA
#define T_gtien t_idmr.7	; global timer interrupt enable
.equiv Tm_oui   , ( 1 <- 0 )		; overflow underflow interrupt mask
.equiv Tm_cm1i  , ( 1 <- 1 )		; Compare 1 interrupt mask
.equiv Tm_cm0i  , ( 1 <- 2 )		; Compare 0 interrupt mask
.equiv Tm_cm0d  , ( 1 <- 3 )		; Compare 0 DMA mask
.equiv Tm_cp1i  , ( 1 <- 4 )		; Capture 1 interrupt mask
.equiv Tm_cp0i  , ( 1 <- 5 )		; Capture 0 interrupt mask
.equiv Tm_cp0d  , ( 1 <- 6 )		; Capture 0 DMA mask
.equiv Tm_gtien , ( 1 <- 7 )		; global timer interrupt enable mask

.equiv T0_DCPR , R240                 ; MFTimer 0 DMA Counter Pointer Register.
t0_dcpr  = r0
.equiv T1_DCPR , R244                 ; MFTimer 1 DMA Counter Pointer Register.
t1_dcpr  = r4
.equiv T0_DAPR , R241                 ; MFTimer 0 DMA Address Pointer Register.
t0_dapr  = r1
.equiv T1_DAPR , R245                 ; MFTimer 1 DMA Address Pointer Register.
t1_dapr  = r5
.equiv T0_IVR  , R242                 ; MFTimer 0 Interrupt Vector Register.
t0_ivr   = r2
.equiv T1_IVR  , R246                 ; MFTimer 1 Interrupt Vector Register.
t1_ivr   = r6
.equiv T0_IDCR , R243                 ; MFTimer 0 Interrupt/DMA Control Register.
t0_idcr  = r3
.equiv T1_IDCR , R247                 ; MFTimer 1 Interrupt/DMA Control Register.
t1_idcr  = r7

.equiv T2_DCPR , R240                 ; MFTimer 2 DMA Counter Pointer Register.
t2_dcpr  = r0
.equiv T3_DCPR , R244                 ; MFTimer 3 DMA Counter Pointer Register.
t3_dcpr  = r4
.equiv T2_DAPR , R241                 ; MFTimer 2 DMA Address Pointer Register.
t2_dapr  = r1
.equiv T3_DAPR , R245                 ; MFTimer 3 DMA Address Pointer Register.
t3_dapr  = r5
.equiv T2_IVR  , R242                 ; MFTimer 2 Interrupt Vector Register.
t2_ivr   = r2
.equiv T3_IVR  , R246                 ; MFTimer 3 Interrupt Vector Register.
t3_ivr   = r6
.equiv T2_IDCR , R243                 ; MFTimer 2 Interrupt/DMA Control Register.
t2_idcr  = r3
.equiv T3_IDCR , R247                 ; MFTimer 3 Interrupt/DMA Control Register.
t3_idcr  = r7

.equiv Tm_plm  , 07h			; Priority level mask
.equiv Tm_swen , 08h			; Swap function enable mask
.equiv Tm_dctd , 10h			; DMA compare transaction destination mask
.equiv Tm_dcts , 20h			; DMA capture transaction source mask
.equiv Tm_cme  , 40h			; Compare 0 end of block mask
.equiv Tm_cpe  , 80h			; Capture 0 end of block mask

.equiv T_IOCR  , R248                 ; MFTimer I/O connection register
t_iocr   = r8
.equiv Tm_sc0  , 01h                  ; TxOUTA and TxINA for even MFTimer
.equiv Tm_sc1  , 02h                  ; TxOUTA and TxINA for odd MFTimer

;****************************
;* Standard Timer Registers *
;****************************

.equiv ST_PG   , 11                   ; Standard Timer registers page

.equiv ST_HR   , R240                 ; counter high value register
st_hr    = r0                   ; counter high value register
.equiv ST_LR   , R241                 ; counter low value register
st_lr    = r1                   ; counter low value register
.equiv ST_PR   , R242                 ; prescaler value register
st_pr    = r2                   ; prescaler value register

.equiv ST_CR   , R243                 ; control register
st_cr    = r3                   ; control register
#define ST_ints  st_cr.2	; interrupt select
#define ST_inen  st_cr.3	; input enable bit
#define ST_cont  st_cr.6	; single/continuos bit
#define ST_st    st_cr.7	; start/stop bit
.equiv STm_out   , ( 3 <- 0 )		; output selection mask
.equiv STm_ints  , ( 1 <- 2 )		; interrupt select mask
.equiv STm_inpen , ( 1 <- 3 )		; input enable mask
.equiv STm_inpmd , ( 3 <- 4 )		; input mode mask
.equiv STm_s_c   , ( 1 <- 6 )		; single/continuous mode mask
.equiv STm_st_sp , ( 1 <- 7 )		; start/stop mask

.equiv STm_out_dis      , 000h        ; output disabled
.equiv STm_out_square   , 001h        ; output square wave, toggle at end of count
.equiv STm_out_0        , 002h        ; output 0 at end of count
.equiv STm_out_1        , 003h        ; output 1 at end of count
.equiv STm_inpts_slim   , 000h        ; standard timer interrupt
.equiv STm_inpts_ext    , 004h        ; external interrupt
.equiv STm_inpen_dis    , 000h        ; input section disable
.equiv STm_inpen_en     , 008h        ; input section enable
.equiv STm_inpmd_evt    , 000h        ; event counter input mode
.equiv STm_inpmd_gate   , 010h        ; gated input mode 
.equiv STm_inpmd_trig   , 020h        ; triggerable input mode
.equiv STm_inpmd_retrig , 030h        ; retriggerable input mode
.equiv STm_s_c_cont     , 000h        ; continuous mode
.equiv STm_s_c_single   , 040h        ; single mode
.equiv STm_st_sp_stop   , 000h        ; stop standard timer
.equiv STm_st_sp_start  , 080h        ; start standard timer

;***************************************************************************

;               ST9 FAMILY FAST A/D CONVERTER REGISTERS.

;***************************************************************************

.equiv FAD_PG  , 62                   ; A/D converter registers page

.equiv FAD_DTR , R240                 ; data register
fad_dtr  = r0                   ; data register
.equiv FAD_CLR , R241                 ; Control logic register
fad_clr  = r1                   ; Control logic register

  #define FAD_str  fad_clr.0  ; start/stop bit
  #define FAD_cont fad_clr.1  ; Continuous mode
  #define FAD_pow  fad_clr.2  ; power enable/disable control
  #define FAD_trg  fad_clr.3  ; external trigger selection
  #define FAD_fs   fad_clr.4  ; fast/slow mode

.equiv FADm_str     , ( 1 <- 0 )      ; start/stop bit mask
.equiv FADm_cont    , ( 1 <- 1 )      ; Continuous mode mask
.equiv FADm_pow     , ( 1 <- 2 )      ; power enable/disable control mask
.equiv FADm_trg     , ( 1 <- 3 )      ; external trigger enable/disable mask
.equiv FADm_fs      , ( 1 <- 4 )      ; fast/slow mode mask
.equiv FADm_channel , ( 7 <- 5 )      ; channel number

.equiv FADm_str_stop        , 000h    ; stop conversion
.equiv FADm_str_start       , 001h    ; start conversion
.equiv FADm_cont_single     , 000h    ; single conversion
.equiv FADm_cont_cont       , 002h    ; continuous conversion
.equiv FADm_pow_dis         , 000h    ; power disable
.equiv FADm_pow_en          , 004h    ; power enable
.equiv FADm_trg_dis         , 000h    ; external trigger disable
.equiv FADm_trg_en          , 008h    ; external trigger (falling edge) enable
.equiv FADm_fs_fast         , 000h    ; fast conversion mode
.equiv FADm_fs_slow         , 010h    ; slow conversion mode

.equiv FAD_INT , R242                 ; AD interrupt register
fad_dtr  = r2                   ; AD interrupt register

  #define FAD_ad_int  fad_int.0  ; ADC interrupt select bit

.equiv FADm_ad_int     , ( 1 <- 0 )      ; ADC interrupt select bit mask

;********************************************
;* Serial Communication Interface Registers *
;********************************************

.equiv SCI0_PG , 24                   ; SCI0 control registers page
.equiv SCI1_PG , 25                   ; SCI1 control registers page
.equiv SCI2_PG , 26                   ; SCI2 control registers page
.equiv SCI3_PG , 27                   ; SCI3 control registers page

.equiv S_RDCPR , R240                 ; receive DMA counter pointer register
s_rdcpr  = r0                   ; receive DMA counter pointer register
.equiv S_RDAPR , R241                 ; receive DMA address pointer register