st92163.inc

用ST92163开发的鼠标

.equiv WDm_inm_t   , 020h             ; TWD input mode triggerable.
.equiv WDm_inm_rt  , 030h             ; TWD input mode retriggerable.

.equiv WCR	, R252			; Wait control register
wcr	 = r12
#define WD_wden  wcr.6        ; TWD timer enable.
#define uds2     wcr.5        ; Upper memory Address strobe Stretch bit 2
#define uds1     wcr.4        ; Upper memory Address strobe Stretch bit 1
#define uds0     wcr.3        ; Upper memory Address strobe Stretch bit 0
#define lds2     wcr.2        ; Lower memory Address strobe Stretch bit 2
#define lds1     wcr.1        ; Lower memory Address strobe Stretch bit 1
#define lds0     wcr.0        ; Lower memory Address strobe Stretch bit 0
.equiv Wm_wdgen , ( 1 <- 6 )          ; TWD timer enable mask
.equiv Wm_uds2  , ( 1 <- 5 )          ; Upper Memory Data Strobe Wait Cycle
.equiv Wm_uds1  , ( 1 <- 4 )
.equiv Wm_uds0  , ( 1 <- 3 )
.equiv Wm_lds2  , ( 1 <- 2 )          ; Lower Memory Data Strobe Wait Cycle
.equiv Wm_lds1  , ( 1 <- 1 )
.equiv Wm_lds0  , ( 1 <- 0 )

.equiv WCR_uds  , ( 7 <- 3 )          ; Upper memory Address strobe Stretch
.equiv WCR_lds  , ( 7 <- 0 )          ; Lower memory Address strobe stretch

.equiv Wm_umwc1 , Wm_uds0             ; 1 wait cycle  on upper M.
.equiv Wm_umwc2 , Wm_uds1             ; 2 wait cycles on upper M.
.equiv Wm_umwc3 , ( Wm_uds1|Wm_uds0 ) ; 3 wait cycles on upper M.
.equiv Wm_umwc4 , Wm_uds2             ; 4 wait cycles on upper M.
.equiv Wm_umwc5 , (Wm_uds2|Wm_uds0)   ; 5 wait cycles on upper M.
.equiv Wm_umwc6 , (Wm_uds2|Wm_uds1)   ; 6 wait cycles on upper M.
.equiv Wm_umwc7 , (Wm_uds2|Wm_uds1|Wm_uds0) ; 7 wait cycles on upper M.

.equiv Wm_lmwc1 ,  Wm_lds0            ; 1 wait cycle  on lower M.
.equiv Wm_lmwc2 ,  Wm_lds1            ; 2 wait cycles on lower M.
.equiv Wm_lmwc3 , (Wm_lds1|Wm_lds0 )  ; 3 wait cycles on lower M.
.equiv Wm_lmwc4 ,  Wm_lds2            ; 4 wait cycles on lower M.
.equiv Wm_lmwc5 , (Wm_lds2|Wm_lds0 )  ; 5 wait cycles on lower M.
.equiv Wm_lmwc6 , (Wm_lds2|Wm_lds1 )  ; 6 wait cycles on lower M.
.equiv Wm_lmwc7 , (Wm_lds2|Wm_lds1|Wm_lds0) ; 7 wait cycles on lower M.

; for ST9OLD

.equiv Wm_wdm2  , ( 1 <- 5 )          ; Data Memory Wait Cycle
.equiv Wm_wdm1  , ( 1 <- 4 ) 
.equiv Wm_wdm0  , ( 1 <- 3 )
.equiv Wm_wpm2  , ( 1 <- 2 )          ; Program Memory Wait Cycle
.equiv Wm_wpm1  , ( 1 <- 1 )
.equiv Wm_wpm0  , ( 1 <- 0 )

.equiv Wm_dmwc1 , Wm_wdm0             ; 1 wait cycle  on Data M.
.equiv Wm_dmwc2 , Wm_wdm1             ; 2 wait cycles on Data M.
.equiv Wm_dmwc3 , ( Wm_wdm1|Wm_wdm0 ) ; 3 wait cycles on Data M.
.equiv Wm_dmwc4 , Wm_wdm2             ; 4 wait cycles on Data M.
.equiv Wm_dmwc5 , (Wm_wdm2|Wm_wdm0)   ; 5 wait cycles on Data M.
.equiv Wm_dmwc6 , (Wm_wdm2|Wm_wdm1)   ; 6 wait cycles on Data M.
.equiv Wm_dmwc7 , (Wm_wdm2|Wm_wdm1|Wm_wdm0) ; 7 wait cycles on Data M.

.equiv Wm_pmwc1 ,  Wm_wpm0            ; 1 wait cycle  on Prog M.
.equiv Wm_pmwc2 ,  Wm_wpm1            ; 2 wait cycles on Prog M.
.equiv Wm_pmwc3 , (Wm_wpm1|Wm_wpm0 )  ; 3 wait cycles on Prog M.
.equiv Wm_pmwc4 ,  Wm_wpm2            ; 4 wait cycles on Prog M.
.equiv Wm_pmwc5 , (Wm_wpm2|Wm_wpm0 )  ; 5 wait cycles on Prog M.
.equiv Wm_pmwc6 , (Wm_wpm2|Wm_wpm1 )  ; 6 wait cycles on Prog M.
.equiv Wm_pmwc7 , (Wm_wpm2|Wm_wpm1|Wm_wpm0) ; 7 wait cycles on Prog M.

;*************************
;* SPI Control Registers *
;*************************

.equiv SPI_PG	, 0                    ; SPI register page

.equiv SPIDR	, R253                 ; SPI Data register
spidr	 = r13

.equiv SPICR	, R254                 ; SPI Control register
spicr	 = r14
#define SP_spen spicr.7	; Serial Peripheral Enable.
#define SP_bms  spicr.6	; SBUS/I2C bus Mode Selector.
#define SP_arb  spicr.5	; Arbitration flag bit.
#define SP_busy spicr.4	; SPI busy flag.
#define SP_cpol spicr.3	; SPI transmission clock polarity
#define SP_cpha spicr.2	; SPI transmission clock phase
#define SP_spr1 spicr.1	; SPI rate bit 1
#define SP_spr0 spicr.0	; SPI rate bit 0
.equiv SPm_spen    , ( 1 <- 7 )       ; Serial Peripheral Enable mask
.equiv SPm_bms     , ( 1 <- 6 )       ; SBUS/I2C bus selector mask
.equiv SPm_arb     , ( 1 <- 5 )       ; Arbitration mask
.equiv SPm_sp_busy , ( 1 <- 4 )       ; SPI busy mask
.equiv SPm_cpol    , ( 1 <- 3 )       ; SPI transmission clock polarity mask
.equiv SPm_cpha    , ( 1 <- 2 )       ; SPI transmission clock phase

.equiv SPm_8       , 0                ; SPI clock divider   8 = 1500 kHz (12MHz)
.equiv SPm_16      , 1                ; SPI clock divider  16 =  750 kHz (12MHz)
.equiv SPm_128     , 2                ; SPI clock divider 128 = 93.75 kHz (12MHz)
.equiv SPm_256     , 3                ; SPI clock divider 256 = 46.87 kHz (12MHz)


;**********************
;* I/O Port Registers *
;**********************
; P0DR, P1DR, P2DR, P3DR are mapped 
; in the system registers if DPRREM=0 in EMR2 register.
; They are mapped in page 21 if DPRREM=1 in EMR2 register

.equiv P0C_PG  , 2                    ; Port 0 control registers page
.equiv P0D_PG  , 21                   ; Port 0 data register page

.equiv P0DR    , R224                 ; Port 0 data register
.equiv P0DR_P  , R240                 ; Port 0 data register
.equiv P0C0R   , R240                 ; Port 0 control register 0
.equiv P0C1R   , R241                 ; Port 0 control register 1
.equiv P0C2R   , R242                 ; Port 0 control register 2
p0dr     = r0
p0dr_p   = r0
p0c0r    = r0
p0c1r    = r1
p0c2r    = r2

.equiv P1C_PG  , 2                    ; Port 1 control registers page
.equiv P1D_PG  , 21                   ; Port 1 data register page

.equiv P1DR    , R225                 ; Port 1 data register
.equiv P1DR_P  , R241                 ; Port 1 data register
.equiv P1C0R   , R244                 ; Port 1 control register 0
.equiv P1C1R   , R245                 ; Port 1 control register 1
.equiv P1C2R   , R246                 ; Port 1 control register 2
p1dr     = r1
p1dr_p   = r1
p1c0r    = r4
p1c1r    = r5
p1c2r    = r6

.equiv P2C_PG  , 2                    ; Port 2 control registers page
.equiv P2D_PG  , 21                   ; Port 2 data register page

.equiv P2DR    , R226                 ; Port 2 data register
.equiv P2DR_P  , R242                 ; Port 2 data register
.equiv P2C0R   , R248                 ; Port 2 control register 0
.equiv P2C1R   , R249                 ; Port 2 control register 1
.equiv P2C2R   , R250                 ; Port 2 control register 2
p2dr     = r2
p2dr_p   = r2
p2c0r    = r8
p2c1r    = r9
p2c2r    = r10

.equiv P3C_PG  , 2                    ; Port 3 control registers page
.equiv P3D_PG  , 21                   ; Port 3 data register page

.equiv P3DR    , R227                 ; Port 3 data register
.equiv P3DR_P  , R243                 ; Port 3 data register
.equiv P3C0R   , R252                 ; Port 3 control register 0
.equiv P3C1R   , R253                 ; Port 3 control register 1
.equiv P3C2R   , R254                 ; Port 3 control register 2
p3dr     = r3
p3dr_p   = r3
p3c0r    = r12
p3c1r    = r13
p3c2r    = r14

.equiv P4C_PG  , 3                    ; Port 4 control registers page

.equiv P4DR    , R228                 ; Port 4 data register
.equiv P4C0R   , R240                 ; Port 4 control register 0
.equiv P4C1R   , R241                 ; Port 4 control register 1
.equiv P4C2R   , R242                 ; Port 4 control register 2
p4dr     = r4
p4c0r    = r0
p4c1r    = r1
p4c2r    = r2

.equiv P5C_PG  , 3                    ; Port 5 control registers page

.equiv P5DR    , R229                 ; Port 5 data register
.equiv P5C0R   , R244                 ; Port 5 control register 0
.equiv P5C1R   , R245                 ; Port 5 control register 1
.equiv P5C2R   , R246                 ; Port 5 control register 2
p5dr     = r5
p5c0r    = r4
p5c1r    = r5
p5c2r    = r6

.equiv P6C_PG  , 3                    ; Port 6 control registers page
.equiv P6D_PG  , 3                    ; Port 6 data register page

.equiv P6DR    , R251                 ; Port 6 data register
.equiv P6C0R   , R248                 ; Port 6 control register 0
.equiv P6C1R   , R249                 ; Port 6 control register 1
.equiv P6C2R   , R250                 ; Port 6 control register 2
p6dr     = r11
p6c0r    = r8
p6c1r    = r9
p6c2r    = r10

.equiv P7C_PG  , 3                    ; Port 7 control registers page
.equiv P7D_PG  , 3                    ; Port 7 data register page

.equiv P7DR    , R255                 ; Port 7 data register
.equiv P7C0R   , R252                 ; Port 7 control register 0
.equiv P7C1R   , R253                 ; Port 7 control register 1
.equiv P7C2R   , R254                 ; Port 7 control register 2
p7dr     = r15
p7c0r    = r12
p7c1r    = r13
p7c2r    = r14

.equiv P8C_PG  , 43                   ; Port 8 control registers page
.equiv P8D_PG  , 43                   ; Port 8 data register page

.equiv P8DR    , R251                 ; Port 8 data register
.equiv P8C0R   , R248                 ; Port 8 control register 0
.equiv P8C1R   , R249                 ; Port 8 control register 1
.equiv P8C2R   , R250                 ; Port 8 control register 2
p8dr     = r11
p8c0r    = r8
p8c1r    = r9
p8c2r    = r10

.equiv P9C_PG  , 43                   ; Port 9 control registers page
.equiv P9D_PG  , 43                   ; Port 9 data register page

.equiv P9DR    , R255                 ; Port 9 data register
.equiv P9C0R   , R252                 ; Port 9 control register 0
.equiv P9C1R   , R253                 ; Port 9 control register 1
.equiv P9C2R   , R254                 ; Port 9 control register 2
p9dr     = r15
p9c0r    = r12
p9c1r    = r13
p9c2r    = r14

.equiv HDCTL2R , R251                 ; Port 2 handshake DMA control register
.equiv HDCTL3R , R255                 ; Port 3 handshake DMA control register
.equiv HDCTL4R , R243                 ; Port 4 handshake DMA control register
.equiv HDCTL5R , R247                 ; Port 5 handshake DMA control register
hdctl2r  = r11
hdctl3r  = r15
hdctl4r  = r3
hdctl5r  = r7

;Handshake DMA control register configuration.

.equiv HDm_hsdis , 0E0h               ; Handshake disabled mask
.equiv HDm_hso2  , 0C0h               ; Handshake output 2 lines mask
.equiv HDm_hso1  , 040h               ; Handshake output 1 line mask
.equiv HDm_hsi2  , 0A0h               ; Handshake input 2 lines mask
.equiv HDm_hsi1  , 020h               ; Handshake input 1 line mask
.equiv HDm_hsb   , 000h               ; Handshake bidirectional mask
.equiv HDm_den   , 000h               ; DMA enable mask
.equiv HDm_ddi   , 010h               ; DMA disable mask
.equiv HDm_ddw   , 000h               ; Data direction output mask (write)
.equiv HDm_ddr   , 008h               ; Data direction input mask (read)
.equiv HDm_dst   , 004h               ; DMA strobe on chip event mask
.equiv HDm_dcp0  , 000h               ; DMA channel capture0 mask
.equiv HDm_dcm0  , 002h               ; DMA channel compare0 mask

;**********************************
;* Multi Function Timer Registers *
;**********************************

.equiv T0D_PG  , 10                   ; MFTimer 0 data registers page
.equiv T0C_PG  , 9                    ; MFTimer 0 control registers page
.equiv T1D_PG  , 8                    ; MFTimer 1 data registers page
.equiv T1C_PG  , 9                    ; MFTimer 1 control registers page
.equiv T2D_PG  , 14                   ; MFTimer 2 data registers page
.equiv T2C_PG  , 13                   ; MFTimer 2 control registers page
.equiv T3D_PG  , 12                   ; MFTimer 3 data registers page
.equiv T3C_PG  , 13                   ; MFTimer 3 control registers page

.equiv T_REG0R	, RR240                ; MFTimer REG0 load and capture register.
t_reg0r  = rr0
.equiv T_REG0HR , R240                ; Register 0 high register
t_reg0hr  = r0
.equiv T_REG0LR , R241                ; Register 0 low register
t_reg0lr  = r1

.equiv T_REG1R , RR242                ; MFTimer REG1 load constant 
t_reg1r  = rr2                  ; and capture register.
.equiv T_REG1HR , R242                ; Register 1 high register
t_reg1hr  = r2
.equiv T_REG1LR , R243                ; Register 1 low register
t_reg1lr  = r3

.equiv T_CMP0R , RR244                ; MFTimer CMP0 store compare constant.
t_cmp0r  = rr4