st92163.inc

用ST92163开发的鼠标

;*****************************************************************************
;*           (c) ST MICROELECTRONICS - All Right Reserved                    *
;*****************************************************************************
;* THE SOFTWARE INCLUDED IN THIS FILE IS FOR GUIDANCE ONLY.                  *
;* ST MICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR  *
;* CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM USE OF THIS *
;* SOFTWARE.                                                                 *
;*===========================================================================*
;*      FILE            :  st90158.inc                                       *
;*      AUTHOR(s)       :  C Baek / Kh Choi of ST-Korea                      *
;*      DATE            :  08/01/99                                          *
;*      PROCESSOR       :  ST90158                                           *
;*      COMPILER        :  GNU C Compiler - V4.3                             *
;*                                                                           *
;*      DESCRIPTION     :  Include file for the definitions                  *
;*			   Registers and Bits of ST90158 family              *
;****************************************************************************/

.nolist

;***********************************
;* REGISTER FILE GROUPS DEFINITION *
;***********************************

.equiv BK00	, 0			; r0 to r7  in group 0
.equiv BK01	, 1			; r8 to r15 in group 0
.equiv BK10	, 2			; r0 to r7  in group 1
.equiv BK11	, 3			; r8 to r15 in group 1
.equiv BK20	, 4			; r0 to r7  in group 2
.equiv BK21	, 5			; r8 to r15 in group 2
.equiv BK30	, 6			; r0 to r7  in group 3
.equiv BK31	, 7			; r8 to r15 in group 3
.equiv BK40	, 8			; r0 to r7  in group 4
.equiv BK41	, 9			; r8 to r15 in group 4
.equiv BK50	, 10			; r0 to r7  in group 5
.equiv BK51	, 11			; r8 to r15 in group 5
.equiv BK60	, 12			; r0 to r7  in group 6
.equiv BK61	, 13			; r8 to r15 in group 6
.equiv BK70	, 14			; r0 to r7  in group 7
.equiv BK71	, 15			; r8 to r15 in group 7
.equiv BK80	, 16			; r0 to r7  in group 8
.equiv BK81	, 17			; r8 to r15 in group 8
.equiv BK90	, 18			; r0 to r7  in group 9
.equiv BK91	, 19			; r8 to r15 in group 9
.equiv BKA0	, 20			; r0 to r7  in group A
.equiv BKA1	, 21			; r8 to r15 in group A
.equiv BKB0	, 22			; r0 to r7  in group B
.equiv BKB1	, 23			; r8 to r15 in group B
.equiv BKC0	, 24			; r0 to r7  in group C
.equiv BKC1	, 25			; r8 to r15 in group C
.equiv BKD0	, 26			; r0 to r7  in group D
.equiv BKD1	, 27			; r8 to r15 in group D
.equiv BKE0	, 28			; r0 to r7  in group E
.equiv BKE1	, 29			; r8 to r15 in group E
.equiv BKF0	, 30			; r0 to r7  in group F
.equiv BKF1	, 31			; r8 to r15 in group F

.equiv BK_SYS	, BKE0			; Group system definition
.equiv BK_F	, BKF0			; page register definition

;********************
;* SYSTEM REGISTERS *
;********************

.equiv FCW	, RR230		; Flags and control word.
fcw	 = rr6

.equiv CICR	, R230			; Central interrupt control register.
cicr	 = r6
#define gcen cicr.7		; Global counter enable.
#define tlip cicr.6		; Top level interrupt pending bit
#define tli  cicr.5		; Top level interrupt bit.
#define ien  cicr.4		; Interrupt enable flag.
#define iam  cicr.3		; Interrupt arbitration mode.
#define cpl2 cicr.2		; Current priority level bit 2.
#define cpl1 cicr.1		; Current priority level bit 1.
#define cpl0 cicr.0		; Current priority level bit 0.
.equiv Im_gcenm , ( 1 <- 7 )          ; Global counter enable bit mask
.equiv Im_tlipm , ( 1 <- 6 )          ; Top level interrupt pending mask.
.equiv Im_tlim	 , ( 1 <- 5 )          ; Top level interrupt mask.
.equiv Im_ienm  , ( 1 <- 4 )          ; Interrupt enable flag mask.
.equiv Im_iamm  , ( 1 <- 3 )          ; Interrupt arbitration mode mask.
.equiv Im_cpl2m , ( 1 <- 2 )          ; Current priority level bit 2 mask.
.equiv Im_cpl1m , ( 1 <- 1 )          ; Current priority level bit 1 mask.
.equiv Im_cpl0m , ( 1 <- 0 )          ; Current priority level bit 0 mask.
.equiv Im_cplm  , (Im_cpl2m|Im_cpl1m|Im_cpl0m ) ; Current priority level

.equiv FLAGR	, R231			; Flags register.
flagr	 = r7
#define c   flagr.7		; Carry flag.
#define z   flagr.6		; Zero flag.
#define s   flagr.5		; Sign flag.
#define v   flagr.4		; Overflow flag.
#define d   flagr.3		; Decimal adjust flag.
#define h   flagr.2		; Half carry flag.
#define uf  flagr.1		; User flag 1.
#define dp  flagr.0		; Data/program memory flag.
.equiv FLm_cm	, ( 1 <- 7 )		; Carry flag mask.
.equiv FLm_zm  , ( 1 <- 6 )		; Zero flag mask.
.equiv FLm_sm  , ( 1 <- 5 )		; Sign flag mask.
.equiv FLm_vm  , ( 1 <- 4 )		; Overflow flag mask.
.equiv FLm_dm  , ( 1 <- 3 )		; Decimal adjust flag mask.
.equiv FLm_hm  , ( 1 <- 2 )		; Half carry flag mask.
.equiv FLm_ufm , ( 1 <- 1 )		; User flag 1 mask.
.equiv FLm_dpm , ( 1 <- 0 )		; Data/program memory mask.

.equiv RPP	, RR232		; Register pointer pair.
rpp	 = rr8

.equiv RP0R	, R232			; Register pointer # 0.
rp0r	 = r8
#define rp0s rp0r.2		; Register pointer selector
.equiv RPm_rp0sm , ( 1 <- 2 )         ; Register pointer selector mask

.equiv RP1R	, R233                 ; Register pointer # 1.
rp1r	 = r9
#define rp1s rp1r.2		; Register pointer selector
.equiv RPm_rp1sm , ( 1 <- 2 )         ; Register pointer selector mask

.equiv PPR	, R234			; Page pointer register.
ppr	 = r10

.equiv MODER	, R235			; Mode register.
moder    = r11
#define ssp   moder.7		; System stack pointer flag (Int/Ext).
#define usp   moder.6		; User stack pointer flag (Int/Ext).
#define div2  moder.5		; External clock divided by 2.
#define prs2  moder.4		; Internal clock prescaling bit 2.
#define prs1  moder.3		; Internal clock prescaling bit 1.
#define prs0  moder.2		; Internal clock prescaling bit 0.
#define brqen moder.1		; Bus request enable.
#define himp  moder.0		; High impedance enable.
.equiv MOm_sspm , ( 1 <- 7 )          ; System stack pointer mask (Int/Ext).
.equiv MOm_uspm , ( 1 <- 6 )          ; User stack pointer mask (Int/Ext).
.equiv MOm_div2m , ( 1 <- 5 )         ; External clock divided by 2 mask.
.equiv MOm_prs2m , ( 1 <- 4 )         ; Internal clock prescaling bit 2 mask.
.equiv MOm_prs1m , ( 1 <- 3 )         ; Internal clock prescaling bit 1 mask.
.equiv MOm_prs0m , ( 1 <- 2 )         ; Internal clock prescaling bit 0 mask.
.equiv MOm_prsm , (MOm_prs2m|MOm_prs1m|MOm_prs0m) ; Internal clock prescaler
.equiv MOm_brqenm , ( 1 <- 1 )        ; Bus request enable mask.
.equiv MOm_himpm , ( 1 <- 0 )         ; High impedence enable mask.

.equiv USPR	, RR236		; User stack pointer.
uspr	 = rr12
.equiv USPHR	, R236			; User stack pointer, msb.
usphr	 = r12
.equiv USPLR	, R237			; User stack pointer, lsb.
usplr    = r13
.equiv SSPR	, RR238		; System stack pointer.
sspr	 = rr14
.equiv SSPHR	, R238			; System stack pointer, msb.
ssphr	 = r14
.equiv SSPLR	, R239			; System stack pointer, lsb.
ssplr	 = r15

;***************************************
;* External Interrupt Control Register *
;***************************************

.equiv EXINT_PG , 0			; EXTERNAL interrupt register page

.equiv EITR	, R242			; External interrupt trigger level register
eitr	 = r2
#define tea0 eitr.0		; Trigger Event A0 bit
#define tea1 eitr.1		; Trigger Event A1 bit
#define teb0 eitr.2		; Trigger Event B0 bit
#define teb1 eitr.3		; Trigger Event B1 bit
#define tec0 eitr.4		; Trigger Event C0 bit
#define tec1 eitr.5		; Trigger Event C1 bit
#define ted0 eitr.6		; Trigger Event D0 bit
#define ted1 eitr.7		; Trigger Event D1 bit
.equiv EIm_tea0m , ( 1 <- 0 )		; Trigger Event A0 mask
.equiv EIm_tea1m , ( 1 <- 1 )		; Trigger Event A1 mask
.equiv EIm_teb0m , ( 1 <- 2 )		; Trigger Event B0 mask
.equiv EIm_teb1m , ( 1 <- 3 )		; Trigger Event B1 mask
.equiv EIm_tec0m , ( 1 <- 4 )		; Trigger Event C0 mask
.equiv EIm_tec1m , ( 1 <- 5 )		; Trigger Event C1 mask
.equiv EIm_ted0m , ( 1 <- 6 )		; Trigger Event D0 mask
.equiv EIm_ted1m , ( 1 <- 7 )		; Trigger Event D1 mask

.equiv EIPR	, R243			; External interrupt pending register
eipr	 = r3
#define ipa0 eipr.0		; Interrupt Pending bit Channel A0
#define ipa1 eipr.1		; Interrupt Pending bit     "   A1
#define ipb0 eipr.2		; Interrupt Pending bit     "   B0
#define ipb1 eipr.3		; Interrupt Pending bit     "   B1
#define ipc0 eipr.4		; Interrupt Pending bit     "   C0
#define ipc1 eipr.5		; Interrupt Pending bit     "   C1
#define ipd0 eipr.6		; Interrupt Pending bit     "   D0
#define ipd1 eipr.7		; Interrupt Pending bit     "   D1
.equiv EIm_ipa0m , ( 1 <- 0 )		; Interrupt Pending A0 mask
.equiv EIm_ipa1m , ( 1 <- 1 )		; Interrupt Pending A1 mask
.equiv EIm_ipb0m , ( 1 <- 2 )		; Interrupt Pending B0 mask
.equiv EIm_ipb1m , ( 1 <- 3 )		; Interrupt Pending B1 mask
.equiv EIm_ipc0m , ( 1 <- 4 )		; Interrupt Pending C0 mask
.equiv EIm_ipc1m , ( 1 <- 5 )		; Interrupt Pending C1 mask
.equiv EIm_ipd0m , ( 1 <- 6 )		; Interrupt Pending D0 mask
.equiv EIm_ipd1m , ( 1 <- 7 )		; Interrupt Pending D1 mask

.equiv EIMR	, R244			; External interrupt mask register
eimr	 = r4
#define ima0 eimr.0		; Int. A0 bit
#define ima1 eimr.1		; Int. A1 bit
#define imb0 eimr.2		; Int. B0 bit
#define imb1 eimr.3		; Int. B1 bit
#define imc0 eimr.4		; Int. C0 bit
#define imc1 eimr.5		; Int. C1 bit
#define imd0 eimr.6		; Int. D0 bit
#define imd1 eimr.7		; Int. D1 bit
.equiv EIm_ia0m , ( 1 <- 0 )		; Int. A0 mask
.equiv EIm_ia1m , ( 1 <- 1 )		; Int. A1 mask
.equiv EIm_ib0m , ( 1 <- 2 )		; Int. B0 mask
.equiv EIm_ib1m , ( 1 <- 3 )		; Int. B1 mask
.equiv EIm_ic0m , ( 1 <- 4 )		; Int. C0 mask
.equiv EIm_ic1m , ( 1 <- 5 )		; Int. C1 mask
.equiv EIm_id0m , ( 1 <- 6 )		; Int. D0 mask
.equiv EIm_id1m , ( 1 <- 7 )		; Int. D1 mask

.equiv EIPLR	, R245			; Ext. interrupt priority level register
eiplr	 = r5
#define pla0 eiplr.0		; Priority Level channel A0 bit
#define pla1 eiplr.1		; Priority Level channel A1 bit
#define plb0 eiplr.2		; Priority Level channel B0 bit
#define plb1 eiplr.3		; Priority Level channel B1 bit
#define plc0 eiplr.4		; Priority Level channel C0 bit
#define plc1 eiplr.5		; Priority Level channel C1 bit
#define pld0 eiplr.6		; Priority Level channel D0 bit
#define pld1 eiplr.7		; Priority Level channel D1 bit
.equiv EIm_plam , ( 3 <- 0 )		; Priority Level group A0,A1
.equiv EIm_plbm , ( 3 <- 2 )		; Priority Level group B0,B1
.equiv EIm_plcm , ( 3 <- 4 )		; Priority Level group C0,C1
.equiv EIm_pldm , ( 3 <- 6 )		; Priority Level group D0,D1

.equiv EIVR	, R246			; External interrupt vector register
eivr	 = r6
#define ewen  eivr.0		; External wait enable
#define ia0s  eivr.1		; Interrupt A0 selection
#define tlis  eivr.2		; Top level input selection
#define tltev eivr.3		; Top level trigger event
.equiv EIm_ewenm , ( 1 <- 0 )		; External wait enable mask
.equiv EIm_iaosm , ( 1 <- 1 )		; Interrupt A0 selection mask
.equiv EIm_tlism , ( 1 <- 2 )		; Top level Input selection mask
.equiv EIm_tltevm , ( 1 <- 3 )	; Top level trigger event mask

.equiv NICR	, R247			; Nested interrupt control register
nicr	 = r7
#define tlnm nicr.7		; Top level not maskable
.equiv EIm_tlnmm , ( 1 <- 7 )		; Top level not maskable mask

;************************************
;* Timer Watchdog Control Registers *
;************************************

.equiv WDT_PG	, 0			; Timer Watchdog page

.equiv WDTR	, RR248		; TWD timer constant register.
wdtr	 = rr8
.equiv WDTHR	, R248			; TWD timer high constant register
wdthr	 = r8
.equiv WDTLR	, R249			; TWD timer low constant register
wdtlr	 = r9
.equiv WDTPR	, R250			; TWD timer prescaler constant register
wdtpr	 = r10

.equiv WDTCR	, R251			; TWD timer control register
wdtcr	 = r11
#define WD_stsp  wdtcr.7	; TWD start stop.
#define WD_sc    wdtcr.6	; TWD single continuous mode.
#define WD_inmd1 wdtcr.5	; Input mode 1
#define WD_inmd2 wdtcr.4	; Input mode 2
#define WD_inen  wdtcr.3	; TWD input section enable/disable.
#define WD_outmd wdtcr.2	; TWD output mode.
#define WD_wrout wdtcr.1	; TWD output bit.
#define WD_outen wdtcr.0	; TWD output enable.
.equiv WDm_stsp    , ( 1 <- 7 )       ; TWD start stop mask
.equiv WDm_sc      , ( 1 <- 6 )       ; TWD single continuous mode mask
.equiv WDm_inen    , ( 1 <- 3 )       ; TWD input section enable/disable mask
.equiv WDm_outmd   , ( 1 <- 2 )       ; TWD output mode mask
.equiv WDm_wrout   , ( 1 <- 1 )       ; TWD output bit mask
.equiv WDm_outen   , ( 1 <- 0 )       ; TWD output enable mask

.equiv WDm_inm_evc , 0                ; TWD input mode event counter.
.equiv WDm_inm_g   , 010h             ; TWD input mode gated.