📄 crtbegin.lis
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350
351
352:../startup/crtbegin.spp **** ld DPR0_P, (rr10)+ ; load page number of start
353 ; address in dpr0
354:../startup/crtbegin.spp **** ldw rr0, (rr10)+ ; load page offset of start
355 ; address of current section
356:../startup/crtbegin.spp **** ldw rr4, (rr10)+ ; size of current section
357:../startup/crtbegin.spp **** ld DPR1_P, (rr10)+ ; load page number of load
358 ; address in dpr1
359:../startup/crtbegin.spp **** ldw rr2, (rr10)+ ; load page offset of load
360 ; address of current section
361:../startup/crtbegin.spp **** or r2, #DPR1_MASK ; ensure 2MSb is dpr1
362
363 LABEL(memory_data_begin):
364
365:../startup/crtbegin.spp **** lddd (rr0)+, (rr2)+ ; copy one byte
366
367:../startup/crtbegin.spp **** dwjxnz rr4, LABEL(memory_data_begin) ; loop while length is not 0
368
369 LABEL(memory_data_end):
370
371 ;
372 ; Init bss-like sections (such .bss section).
373 ; Such section is initialized with the 0 value.
374 ;
375
376 LABEL(memory_bss_init):
377
378:../startup/crtbegin.spp **** btjxf r8.2, LABEL(memory_bss_end)
379
380
381:../startup/crtbegin.spp **** ld DPR0_P, (rr10)+ ; load page number of start
382 ; address in dpr0
383:../startup/crtbegin.spp **** ldw rr0, (rr10)+ ; page offset of start address
384 ; of current section
385
386:../startup/crtbegin.spp **** ldw rr4, (rr10)+ ; size of current section
387:../startup/crtbegin.spp **** ld r3, (rr10)+ ; fill value
388
389 LABEL(memory_bss_begin):
390
391:../startup/crtbegin.spp **** ld (rr0)+, r3 ; set one byte at memory (rr0)
392:../startup/crtbegin.spp **** dwjxnz rr4, LABEL(memory_bss_begin) ; loop while length is not 0
393
394 LABEL(memory_bss_end):
395
396 ;
397 ; Init data-like section in R-file (such .reg8_data section)
398 ; Such section initialization relies on the AT mechanism of ld
399 ;
400
401 LABEL(rfile_data_init):
402
403:../startup/crtbegin.spp **** btjxf r8.3, LABEL(rfile_data_end)
404
405:../startup/crtbegin.spp **** ldw rr0, (rr10)+ ; r0 = first register number
406 ; r1 = size of current section
407
408:../startup/crtbegin.spp **** ld DPR0_P, (rr10)+ ; load page number of load
409 ; address in dpr1
410:../startup/crtbegin.spp **** ldw rr2, (rr10)+ ; page offset of load address
411 ; of current section
412
GAS LISTING C:\DOCUME~1\REF\LOCALS~1\Temp\cc001908.s page 14
ST9+ Family: Reset and Clock Control Unit (RCCU) control registers.
413 LABEL(rfile_data_begin):
414
415:../startup/crtbegin.spp **** ld (r0)+, (rr2)+ ; copy one byte in R-file from
416 ; memory
417:../startup/crtbegin.spp **** djxnz r1, LABEL(rfile_data_begin) ; loop while length is not 0
418
419 LABEL(rfile_data_end):
420
421 ;
422 ; Init bss-like section in R-file (such .reg8_bss section)
423 ; Such section is initialized with the 0 value.
424 ; (see note of bss initialization section).
425 ;
426
427 LABEL(rfile_bss_init):
428
429:../startup/crtbegin.spp **** btjxf r8.4, LABEL(rfile_bss_end)
430
431:../startup/crtbegin.spp **** ldw rr0, (rr10)+ ; r0 = first register number
432 ; r1 = size of current section
433:../startup/crtbegin.spp **** ld r2, (rr10)+ ; fill value
434
435 LABEL(rfile_bss_begin):
436
437:../startup/crtbegin.spp **** ld (r0), r2 ; set one byte in R-file
438:../startup/crtbegin.spp **** inc r0 ; increment counter
439:../startup/crtbegin.spp **** djxnz r1, LABEL(rfile_bss_begin) ; loop while length is not 0
440
441 LABEL(rfile_bss_end):
442
443 ;
444 ; Initialize registers which have a fixed numbers.
445 ;
446
447 LABEL(rfile_explicit_init):
448
449:../startup/crtbegin.spp **** btjxf r8.5, LABEL(rfile_explicit_end)
450
451:../startup/crtbegin.spp **** ldw rr0, (rr10)+ ; r0 = first register number
452 ; r1 = size of value
453
454 LABEL(rfile_explicit_begin):
455:../startup/crtbegin.spp **** ld (r0)+, (rr10)+ ; copy one byte at a time
456:../startup/crtbegin.spp **** djxnz r1, LABEL(rfile_explicit_begin) ; loop while length is not 0
457
458 LABEL(rfile_explicit_end):
459
460 ;
461 ; Each entry within the secinfo table is fully located
462 ; within a page. This entry type forces the secinfo table
463 ; pointer to align itself on the next page by increasing
464 ; page number (in dpr2) and set offset to 0.
465 ;
466
467 LABEL(page_switch_init):
468
469:../startup/crtbegin.spp **** btjxf r8.6, LABEL(page_switch_end)
470
471:../startup/crtbegin.spp **** inc DPR2_P ; point on next page
472:../startup/crtbegin.spp **** xor r11, r11 ; load address of secinfo table
473:../startup/crtbegin.spp **** ld r10, #DPR2_MASK ; secinfo table uses dpr2
474
475 LABEL(page_switch_end):
GAS LISTING C:\DOCUME~1\REF\LOCALS~1\Temp\cc001908.s page 15
ST9+ Family: Reset and Clock Control Unit (RCCU) control registers.
476
477 LABEL(sections_fini):
478
479:../startup/crtbegin.spp **** btjxf r8.0, LABEL(sections_begin)
480
481 #endif /* HAS_SECINFO */
482
483 /* +------------------------------------------------------------+
484 | PART 6 : MMU SETUP |
485 +------------------------------------------------------------+ */
486
487 #if defined(MEDIUM)
488
489 ;
490 ; Initialisation of registers controlling external memory interface
491 ; EMR1 reset value is x000-000M
492 ; MC, DS2EN, ASAF, NMB, ET0, BSZ should be checked against user
493 ; memory configuration and EMR1 set accordingly
494 ;
495 ; EMR2 reset value is M000-1111
496 ; ENCSR is 0, which selects ST9 compatibility mode for interrupt handling.
497 ; DMEMSEL, PAS1, PAS0, DAS1 and DAS0 should be checked against user memory
498 ; configuration and set complementarily to WCR in page #0 (see below)
499 ; DPRREM is forced to one to have DPRi registers accessible in group E
500 ;
501
502 or EMR2, #EMR2_dprrem ; remap data page registers
503
504 ;
505 ; Initialization of DPR registers with initial value
506 ;
507
508 ld DPR0, #_idpr0
509 ;
510 ; ST9+V6_TUTORIAL: beginning of modification
511 ; The following lines are commented
512 ;
513 ; ld DPR1, #_idpr1
514 ; ld DPR2, #_idpr2
515 ;
516 ; ST9+V6_TUTORIAL: end of modification
517 ;
518 ld DPR3, #_idpr3
519
520 #else /* MEDIUM */
521
522 ;
523 ; Initialization of DPR registers with initial values
524 ;
525
526:../startup/crtbegin.spp **** ld DPR0_P, #_idpr0
527:../startup/crtbegin.spp **** ld DPR1_P, #_idpr1
528:../startup/crtbegin.spp **** ld DPR2_P, #_idpr2
529:../startup/crtbegin.spp **** ld DPR3_P, #_idpr3
530:../startup/crtbegin.spp **** ld ISR, CSR
531
532 #endif /* MEDIUM */
533
534 #if defined(MEDIUM) || defined (SPECMED)
535
536 ; ENCSR is 1, use CSR for interrupt handling.
537
538 or EMR2, #EMR2_encsr ; enable csr during interrupts
GAS LISTING C:\DOCUME~1\REF\LOCALS~1\Temp\cc001908.s page 16
ST9+ Family: Reset and Clock Control Unit (RCCU) control registers.
539
540 #endif /* MEDIUM */
541
542 #if defined(COMPACT)
543
544 ; in compact programming model, the startup file
545 ; will assumes that CSR = ISR, set by the bootrom
546
547 #endif /* COMPACT */
548
549 .endproc
550
551 /* +------------------------------------------------------------+
552 | PART 7 : CALL MAIN |
553 +------------------------------------------------------------+ */
554
555 .global __initialize_end
556 .global ___initialize_end
557
558 .proc __initialize_end
559
560 __initialize_end:
561 ___initialize_end:
562
563 ;
564 ; Call the main routine
565 ;
566
567:../startup/crtbegin.spp **** _call M_(main)
568
569 .endproc
570
571 /* +------------------------------------------------------------+
572 | PART 8 : TERMINATION |
573 +------------------------------------------------------------+ */
574
575 .global __terminate_begin
576 .global ___terminate_begin
577
578 __terminate_begin:
579 ___terminate_begin:
580
581 .global __terminate_end
582 .global ___terminate_end
583
584 __terminate_end:
585 ___terminate_end:
586
587 .global __Halt
588 .global ___Halt
589
590 .proc __Halt
591
592 __Halt:
593 ___Halt:
594
595:../startup/crtbegin.spp **** jr . ; loop forever
596
597 .endproc
598
599 ;
600 ; End of start-up file end
601 ;
GAS LISTING C:\DOCUME~1\REF\LOCALS~1\Temp\cc001908.s page 17
ST9+ Family: Reset and Clock Control Unit (RCCU) control registers.
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