📄 crtbegin.lis
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ST9+ Family: External Interrupts, Timer Watchdog
7 *
8 * This file describes Core control registers.
9 *
10 * Register Group: E
11 *
12 * Device: any
13 *
14 */
15
16 #ifndef _SYS_SYSTEM_SPP
17 #define _SYS_SYSTEM_SPP
18
19 .sbttl "ST9+ Family: Core control registers."
20
219 .list
220
221 #endif /* !_SYS_SYSTEM_SPP */
222 ...
135
136 #include <sys/mmu.spp>
1 /*
2 * mmu.spp
3 *
4 * ST9+ Software Development Toolchain - Version 6.1.3 Sep 10 2001
5 *
6 * This file is part of GNU C Compiler for ST9+ Micro-controllers.
7 *
8 * This file describes MMU control registers.
9 *
10 * Register Page: 21
11 *
12 * Device: any
13 *
14 */
15
16 #ifndef _SYS_MMU_SPP
17 #define _SYS_MMU_SPP
18
19 .sbttl "ST9+ Family: MMU control registers."
20
136 .list
137
138 #endif /* !_SYS_MMU_SPP */
139 ...
137 #include <sys/rccu.spp>
1 /*
2 * rccu.spp
3 *
4 * ST9+ Software Development Toolchain - Version 6.1.3 Sep 10 2001
5 *
6 * This file is part of GNU C Compiler for ST9+ Micro-controllers.
7 *
8 * This file describes Reset and Clock Control Unit (RCCU) control registers.
9 *
10 * Register Page: 55
11 *
12 * Device: any
13 *
14 */
15
16 #ifndef _SYS_RCCU_SPP
17 #define _SYS_RCCU_SPP
18
GAS LISTING C:\DOCUME~1\REF\LOCALS~1\Temp\cc001908.s page 6
ST9+ Family: MMU control registers.
19 .sbttl "ST9+ Family: Reset and Clock Control Unit (RCCU) control registers."
20
85 .list
86
87 #endif /* !_SYS_RCCU_SPP */
88 ...
138
139 PROGRAMMING_MODEL
140
141 ;
142 ; Start initialization process
143 ;
144
145 .section .init
146
147 .global __initialize_begin
148 .global ___initialize_begin
149
150 __initialize_begin:
151 ___initialize_begin:
152
153 /* +------------------------------------------------------------+
154 | PART 2 : INTERRUPT VECTOR DECLARATION |
155 +------------------------------------------------------------+ */
156
157 ;
158 ; Interrupt vector definition
159 ; Absolute address 0 is assumed (. == 0x0000)
160 ;
161
162 0000 0104 .word __Reset ; address of reset routine
163
164 0002 0100 .word DIVIDE_BY_ZERO_TRAP_LABEL ; address of the divide by zero
165 ; trap routine
166
167 .rept 13
168 .word __Default_Interrupt_Handler
169 .endr
170 0004 01030103
170 01030103
170 01030103
170 01030103
170 01030103
171 001e 0000 .word usb_int
172 0020 0000 .word ep0_int
173 0022 0000 .word ep1_int
174
175 0024 0000 .word ep2_int
176 0026 0000 .word ep3_int
177
178 0028 0000 .word ep4_int
179 002a 0000 .word ep5_int
180
181 002c 0000 .word ep6_int
182 002e 0000 .word ep7_int
183
184 .rept 104
185 .word __Default_Interrupt_Handler
186 .endr
187 0030 01030103
187 01030103
187 01030103
187 01030103
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ST9+ Family: Reset and Clock Control Unit (RCCU) control registers.
187 01030103
188 ;
189 ; ST9+V6_TUTORIAL: end of modification
190 ;
191
192 /* +------------------------------------------------------------+
193 | PART 3 : DEFAULT HANDLERS |
194 +------------------------------------------------------------+ */
195
196 /* Definition of the default divide-by-zero trap
197 handler. */
198
199 #if !defined(DIVIDE_BY_ZERO_TRAP)
200
201 .global CONCATIFY(_,DIVIDE_BY_ZERO_TRAP_DEFAULT)
202 .global DIVIDE_BY_ZERO_TRAP_DEFAULT
203
204 .proc DIVIDE_BY_ZERO_TRAP_DEFAULT
205
206 CONCATIFY(_,DIVIDE_BY_ZERO_TRAP_DEFAULT):
207 DIVIDE_BY_ZERO_TRAP_DEFAULT:
208
209:../startup/crtbegin.spp **** jx __Halt ; loop forever
210
211 .endproc
212
213 #endif /* !DIVIDE_BY_ZERO_TRAP */
214
215 /* Definition of the default routine handler. */
216
217 .global ___Default_Interrupt_Handler
218 .global __Default_Interrupt_Handler
219
220 .proc __Default_Interrupt_Handler
221
222 ___Default_Interrupt_Handler:
223 __Default_Interrupt_Handler:
224
225:../startup/crtbegin.spp **** iret ; just return from interrupt
226
227 .endproc
228
229 /* +------------------------------------------------------------+
230 | PART 4 : SYSTEM SETUP |
231 +------------------------------------------------------------+ */
232
233 .global __Reset
234 .global ___Reset
235
236 ;
237 ; Reset routine
238 ;
239
240 .proc __Reset
241
242 __Reset:
243 ___Reset:
244
245 ;
246 ; WCR = 0x42 => 2 wait state for lower memory + watchdog disabled
247 ;
248
249 #if !defined(INIT_WCR)
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ST9+ Family: Reset and Clock Control Unit (RCCU) control registers.
250 #define INIT_WCR 0x42
251 #endif /* !INIT_WCR */
252:../startup/crtbegin.spp **** spp #WDT_PG ; select register page 0
253:../startup/crtbegin.spp **** ld WCR, #INIT_WCR ; WCR = zero wait state
254
255 ;
256 ; System registers initialization in group 0xE (R224 to R239)
257 ; init clock mode and select external stacks in data memory
258 ; Set register pointer to group 0xD
259 ;
260 ; CICR = IT disabled + Nested Mode + CPL = 7
261 ; MODER = both stacks in memory + clock divided by 2
262 ;
263
264 #if !defined(INIT_CICR)
265 ; #define INIT_CICR 0x8f
266 #define INIT_CICR 0x87
267 #endif /* !INIT_CICR */
268
269 ;
270 ; MODER = 0x00 => oscill clock divided by 1
271 ;
272
273 #if !defined(INIT_MODER)
274 #define INIT_MODER 0x00
275 #endif /* !INIT_MODER */
276
277:../startup/crtbegin.spp **** ld MODER, #INIT_MODER ; init clock and select external
278 ; stacks
279:../startup/crtbegin.spp **** ld CICR, #INIT_CICR ; disable interrupt
280:../startup/crtbegin.spp **** srp #0x1a ; working register in group D
281
282 ;
283 ; Using data memory mode by default
284 ;
285
286:../startup/crtbegin.spp **** sdm ; select data memory
287
288 ;
289 ; Initialize system stack pointer
290 ;
291
292:../startup/crtbegin.spp **** ldw SSPR, #dpr:pof(_stack_end) ; setup system stack pointer
293
294 #if defined(PARMUSP)
295
296 ;
297 ; Routine parameters are passed by user stack pointer.
298 ; Initialize user stack pointer
299 ;
300
301 ldw USPR, #dpr:pof(_user_stack_end) ; setup user system stack
302 ; pointer
303
304 #endif /* PARMUSP */
305
306
307:../startup/crtbegin.spp **** spp #MMU_PG ; select register page 0 [MMU]
308
309 /* +------------------------------------------------------------+
310 | PART 5 : MEMORY/REGISTER FILE INITIALIZATION |
311 +------------------------------------------------------------+ */
312
GAS LISTING C:\DOCUME~1\REF\LOCALS~1\Temp\cc001908.s page 9
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