main.c

基于visual dsp++开发环境

#include "main.h"


// set up DMA descriptors (one for each frame, then repeat)
// small descriptor model, only start address needs to be fetched

tDMA_descriptor DMA_PPI0_first = 	{&DMA_PPI0_second, sFrame0};
tDMA_descriptor DMA_PPI0_second = 	{&DMA_PPI0_third , sFrame1};
tDMA_descriptor DMA_PPI0_third = 	{&DMA_PPI0_fourth, sFrame2};
tDMA_descriptor DMA_PPI0_fourth = 	{&DMA_PPI0_first , sFrame3};


volatile int current_in_Frame  = -1;		// 0, 1, 2 or 3  ... indicates the last frame that was received COMPLETELY

bool Set_DMA32 = false;
bool Set_Entire_Field = false;


// User program
void main() {

	// unblock Core B if dual core operation is desired	
#ifndef RUN_ON_SINGLE_CORE
	*pSICA_SYSCR &= 0xFFDF; // clear bit 5 to unlock  
#endif

	// set Clocks
	Set_PLL( (short)(CORECLK/CLKIN), (short)(CORECLK/SYSCLK));			// sets Core and System Clocks to the values defined in system.h 

	// initialise SDRAM
	InitSDRAM();
	*pTC_PER = 0x0770;			// set DMA traffic control register to favour unidirectional transfers to SDRAM

	
	// initialise PPI0 and associated DMA channel for ADC INPUT
	current_in_Frame  = -1;				// no frames received yet
	semaphore_frames_received = false;	// do not start output stream yet


	Set_DMA32 = false;
#ifdef DMA_32
	Set_DMA32 = true;
#endif
	
	InitPPI0(Set_DMA32, &DMA_PPI0_first, Lower_Blocksize, Upper_Blocksize);
	

		
	// initialise Interrupts
	InitInterrupts_coreA();
	
	
	// enable transfers
	*pDMA1_0_CONFIG |= DMAEN;
	ssync();
	*pPPI0_CONTROL |= PORT_EN;
	ssync();
//	printf("Core #%d Started input stream!\n", &_CORE);


	
	// main loop, just wait for interrupts
	while(1) {
		idle();		//   do nothing
	}	// while(1)
		
	
}		// main