📄 main.c
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#include "main.h"
// set up DMA descriptors (one for each frame, then repeat)
// small descriptor model, only start address needs to be fetched
tDMA_descriptor DMA_PPI1_first = {&DMA_PPI1_second, sFrame0};
tDMA_descriptor DMA_PPI1_second = {&DMA_PPI1_third , sFrame1};
tDMA_descriptor DMA_PPI1_third = {&DMA_PPI1_fourth, sFrame2};
tDMA_descriptor DMA_PPI1_fourth = {&DMA_PPI1_first , sFrame3};
volatile int current_out_Frame = -1; // 0, 1, 2 or 3 ... indicates the last frame that is output COMPLETELY
bool Set_DMA32 = false;
// User program
void main() {
// set Clocks
Set_PLL( (short)(CORECLK/CLKIN), (short)(CORECLK/SYSCLK)); // sets Core and System Clocks to the values defined in system.h
// initialise PPI1 and associated DMA channel for DAC OUTPUT
current_out_Frame = -1; // no frames transmitted yet
Set_DMA32 = false;
#ifdef DMA_32
Set_DMA32 = true;
#endif
InitPPI1(Set_DMA32, &DMA_PPI1_first, Lower_Blocksize, Upper_Blocksize);
// initialise Interrupts
InitInterrupts_coreB();
// now ready to kick off PPI output stream.
// Just wait for core A to indicate that a valid frame has been received
while (!semaphore_frames_received); // loop until core A sets the semaphore
semaphore_frames_received = false;
// start transfers
*pDMA1_1_CONFIG |= DMAEN;
ssync();
*pPPI1_CONTROL |= PORT_EN;
ssync();
if ( (*pDSPID & 0x000FFFF ) < 0x0002)
*pTIMER10_CONFIG = *pTIMER10_CONFIG; // need to write again after enabling PPI1 for Rev <=0.1
ssync();
*pTMRS4_ENABLE |= TIMEN10; //enable Timer and kick off PPI1
ssync();
// printf("Core #%d Started output stream!\n", &_CORE);
// main loop, just wait for interrupts
while(1) {
idle(); // do nothing
} // while(1)
} // main
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