📄 1000406_aa0203-2006_m29w320_u24.ldf
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/* MANAGED-BY-SYSTEM-BUILDER *//*** ADSP-BF538 linker description file generated on Jan 02, 2008 at 22:58:45.**** Copyright (C) 2000-2006 Analog Devices Inc., All Rights Reserved.**** This file is generated automatically based upon the options selected** in the LDF Wizard. Changes to the LDF configuration should be made by ** changing the appropriate options rather than editing this file. **** Configuration:-** crt_doj: .\Debug\1000406_AA0203-2006_M29W320_U24_basiccrt.doj** processor: ADSP-BF538** si_revision: automatic** using_cplusplus: true** mem_init: false** use_vdk: false** use_eh: true** use_argv: false** user_heap_src_file: C:\Build Tools\ant_build\cvsStage\_4.5ExportBlackfinReGen\Examples\Blackfin\Examples\ADSP-BF538F EZ-KIT Lite\Power_On_Self_Test\1000406_AA0203-2006_M29W320_U24_heaptab.c** libraries_use_stdlib: true** libraries_use_fileio_libs: false** libraries_use_ieeefp_emulation_libs: false** libraries_use_eh_enabled_libs: false** system_heap: L1** system_heap_min_size: 2K** system_stack: L1** system_stack_min_size: 2K** use_sdram: true** use_sdram_size: 64M** use_sdram_partitioned: custom***/ARCHITECTURE(ADSP-BF538)SEARCH_DIR($ADI_DSP/Blackfin/lib)// Workarounds are enabled, exceptions are disabled.#define RT_LIB_NAME(x) lib ## x ## y.dlb#define RT_LIB_NAME_EH(x) lib ## x ## y.dlb#define RT_LIB_NAME_MT(x) lib ## x ## y.dlb#define RT_LIB_NAME_EH_MT(x) lib ## x ## y.dlb#define RT_OBJ_NAME(x) x ## y.doj#define RT_OBJ_NAME_MT(x) x ## mty.doj$LIBRARIES = RT_LIB_NAME_MT(small532) ,RT_LIB_NAME_MT(io532) ,RT_LIB_NAME_MT(c532) ,RT_LIB_NAME_MT(event532) ,RT_LIB_NAME_MT(x532) ,RT_LIB_NAME_EH_MT(cpp532) ,RT_LIB_NAME_EH_MT(cpprt532) ,RT_LIB_NAME(f64ieee532) ,RT_LIB_NAME(dsp532) ,RT_LIB_NAME(sftflt532) ,RT_LIB_NAME(etsi532) ,RT_LIB_NAME(ssl538) ,RT_LIB_NAME(drv538) ,RT_OBJ_NAME_MT(idle532) ,RT_LIB_NAME_MT(rt_fileio532) ;$OBJECTS = ".\Debug\1000406_AA0203-2006_M29W320_U24_basiccrt.doj" , RT_LIB_NAME(profile532) , $COMMAND_LINE_OBJECTS , "cplbtab538.doj" , RT_OBJ_NAME(crtn532) ;$OBJS_LIBS_INTERNAL = /*$VDSG<insert-libraries-internal> *//* Text inserted between these $VDSG comments will be preserved *//*$VDSG<insert-libraries-internal> */ $OBJECTS{prefersMem("internal")}, $LIBRARIES{prefersMem("internal")}/*$VDSG<insert-libraries-internal-end> *//* Text inserted between these $VDSG comments will be preserved *//*$VDSG<insert-libraries-internal-end> */ ;$OBJS_LIBS_NOT_EXTERNAL = /*$VDSG<insert-libraries-not-external> *//* Text inserted between these $VDSG comments will be preserved *//*$VDSG<insert-libraries-not-external> */ $OBJECTS{!prefersMem("external")}, $LIBRARIES{!prefersMem("external")}/*$VDSG<insert-libraries-not-external-end> *//* Text inserted between these $VDSG comments will be preserved *//*$VDSG<insert-libraries-not-external-end> */ ;/*$VDSG<insert-user-macros> *//* Text inserted between these $VDSG comments will be preserved *//*$VDSG<insert-user-macros> *//*$VDSG<customise-async-macros> *//* This code is preserved if the LDF is re-generated. */#define ASYNC0_MEMTYPE RAM#define ASYNC1_MEMTYPE RAM#define ASYNC2_MEMTYPE RAM#define ASYNC3_MEMTYPE RAM/*$VDSG<customise-async-macros> */MEMORY{/*** ADSP-BF538 MEMORY MAP.**** The known memory spaces are as follows:**** 0xFFE00000 - 0xFFFFFFFF Core MMR registers (2MB)** 0xFFC00000 - 0xFFDFFFFF System MMR registers (2MB)** 0xFFB01000 - 0xFFBFFFFF Reserved** 0xFFB00000 - 0xFFB00FFF Scratch SRAM (4K)** 0xFFA14000 - 0xFFAFFFFF Reserved** 0xFFA10000 - 0xFFA13FFF Code SRAM / cache (16K)** 0xFFA00000 - 0xFFA0FFFF Code SRAM (64K)** 0xFF908000 - 0xFF9FFFFF Reserved** 0xFF904000 - 0xFF907FFF Data Bank B SRAM / cache (16K)** 0xFF900000 - 0xFF903FFF Data Bank B SRAM (16K)** 0xFF808000 - 0xFF8FFFFF Reserved** 0xFF804000 - 0xFF807FFF Data Bank A SRAM / cache (16K)** 0xFF800000 - 0xFF803FFF Data Bank A SRAM (16K)** 0xEF000000 - 0xFF7FFFFF Reserved** 0x20400000 - 0xEEFFFFFF Reserved** 0x20300000 - 0x203FFFFF ASYNC MEMORY BANK 3 (1MB)** 0x20200000 - 0x202FFFFF ASYNC MEMORY BANK 2 (1MB)** 0x20100000 - 0x201FFFFF ASYNC MEMORY BANK 1 (1MB)** 0x20000000 - 0x200FFFFF ASYNC MEMORY BANK 0 (1MB)** 0x00000000 - 0x07FFFFFF SDRAM MEMORY (16MB - 128MB)**** Notes:** 0xFF807FEF-0xFF807FFF** Required by boot-loader and cannot contain initialized data or code.*/ MEM_SYS_MMRS { TYPE(RAM) START(0xFFC00000) END(0xFFDFFFFF) WIDTH(8) } MEM_L1_SCRATCH { TYPE(RAM) START(0xFFB00000) END(0xFFB00FFF) WIDTH(8) } MEM_L1_CODE { TYPE(RAM) START(0xFFA00000) END(0xFFA13FFF) WIDTH(8) } MEM_L1_DATA_B { TYPE(RAM) START(0xFF900000) END(0xFF907FFF) WIDTH(8) } MEM_L1_DATA_A { TYPE(RAM) START(0xFF800000) END(0xFF807FFF) WIDTH(8) } MEM_ASYNC3 { TYPE(ASYNC3_MEMTYPE) START(0x20300000) END(0x203FFFFF) WIDTH(8) } MEM_ASYNC2 { TYPE(ASYNC2_MEMTYPE) START(0x20200000) END(0x202FFFFF) WIDTH(8) } MEM_ASYNC1 { TYPE(ASYNC1_MEMTYPE) START(0x20100000) END(0x201FFFFF) WIDTH(8) } MEM_ASYNC0 { TYPE(ASYNC0_MEMTYPE) START(0x20000000) END(0x200FFFFF) WIDTH(8) } /*$VDSG<customise-sdram-mem-partition> */ /* This code is preserved if the LDF is re-generated. */ MEM_SDRAM0_BANK0 { TYPE(RAM) START(0x00000004) END(0x00ffffff) WIDTH(8) } MEM_SDRAM0_BANK1 { TYPE(RAM) START(0x01000000) END(0x01ffffff) WIDTH(8) } MEM_SDRAM0_BANK2 { TYPE(RAM) START(0x02000000) END(0x02ffffff) WIDTH(8) } MEM_SDRAM0_BANK3 { TYPE(RAM) START(0x03000000) END(0x03ffffff) WIDTH(8) } /*$VDSG<customise-sdram-mem-partition> */ /*$VDSG<insert-new-memory-segments> */ /* Text inserted between these $VDSG comments will be preserved */ /*$VDSG<insert-new-memory-segments> */ } /* MEMORY */PROCESSOR p0{ OUTPUT($COMMAND_LINE_OUTPUT_FILE) RESOLVE(start, 0xFFA00000) KEEP(start,_main) SECTIONS { /* Workaround for hardware errata 05-00-0189 - ** "Speculative (and fetches made at boundary of reserved memory ** space) for instruction or data fetches may cause false ** protection exceptions". ** ** Done by avoiding use of 76 bytes from at the end of blocks ** that are adjacent to reserved memory. Workaround is enabled ** for appropriate silicon revisions (-si-revision switch). */ RESERVE(___wab0=MEMORY_END(MEM_L1_SCRATCH) - 75, ___l0 = 76) RESERVE(___wab2=MEMORY_END(MEM_L1_CODE) - 75, ___l2 = 76) RESERVE(___wab4=MEMORY_END(MEM_L1_DATA_B) - 75, ___l4 = 76) RESERVE(___wab6=MEMORY_END(MEM_L1_DATA_A) - 75, ___l6 = 76) RESERVE(___wab7=MEMORY_END(MEM_ASYNC3) - 75, ___l7 = 76) RESERVE(___wab8=MEMORY_END(MEM_SDRAM0_BANK3) - 75, ___l8 = 76) /*$VDSG<insert-new-sections-at-the-start> */ /* Text inserted between these $VDSG comments will be preserved */ /*$VDSG<insert-new-sections-at-the-start> */ scratchpad { INPUT_SECTION_ALIGN(4)
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