pll.c

基于visual dsp++开发环境

/*****************************************************************************
**																			**
**	 Name: 	PLL.c															**
**																			**
******************************************************************************

(C) Copyright 2006 - Analog Devices, Inc.  All rights reserved.

Project Name:	BF538F POST ATE

Date Modified:	01 Sept 2006

Software:		VisualDSP++ 4.5

Hardware:		ADSP-BF538F EZ-KIT Lite

Connections:

Purpose:		Setup the core and system clock

*****************************************************************************/
#include <cdefBF538.h>
#include <ccblkfn.h>




void Init_PLL(void)
{
	*pSIC_IWR |= 0x1;			// enable PLL wakeup
	*pPLL_CTL = SET_MSEL(20);	/* (25MHz Xtal x (MSEL=20))::CCLK=500MHz		*/

	idle();

	*pPLL_DIV = SET_SSEL(4);	/* (500MHz/(SSEL=4))::SCLK=125MHz				*/
	ssync();
	*pVR_CTL = 0x00DB;
	ssync();
}