cacheinit.asm

基于visual dsp++开发环境

/*****************************************************************************
**																			**
**	 Name: 	Cache_Example.dpj							        			**	
**																			**
******************************************************************************

(C) Copyright 2003 - Analog Devices, Inc.  All rights reserved.

File Name:		cacheinit.asm

Date Modified:	11/21/05		JM		Rev 2.0

Comments:		Added init of DAG registers: m2, l2 and b2
				Replaced "csync" by "ssync" before "rts"
				
				Added workaround to anomaly 05000258

Software:       VisualDSP++ 4.0 (September 2005 Update)

Hardware:		ADSP-BF537 EZ-KIT Board

Special Connections:  None

Purpose:		To demonstrate configuring and enabling cache features.
				
Program Parameters:

******************************************************************************/


#include <defBF537.h>



/***************************************************************

	Cache initialization routine
	
	This routine sets up data and/or instruction cache based on 
	the #defines in cache_init.h
***************************************************************/

#include "cache_init.h"


.section L1_code;
.align 4;

.global cache_init;
cache_init:

#ifdef INSTR_CACHE_EN

	m0=0(z); m1=0(z); m2=0(z);
	l0=0(z); l1=0(z); l2=0(z);
	b0=0(z); b1=0(z); b2=0(z);

//  Initialize INSTRUCTION CPLBs
	i0.l = lo(ICPLB_ADDR0);
	i0.h = hi(ICPLB_ADDR0);

	i1.l = lo(ICPLB_DATA0);
	i1.h = hi(ICPLB_DATA0);

	i2.l = icplbs_table;
	i2.h = icplbs_table;

	r1 = -1;  	// end point comparison 
	r3 = 15;	// max counter 

// read entries from table 
	read_iaddr:
		r0 = [i2++];
		cc = r0 == r1;
		if cc jump idone;
		[i0++] = r0;
	read_idata:
		r2 = [i2++];
		[i1++] = r2;
		r3 = r3 + r1;
		cc = r3 == r1;
		if !cc jump read_iaddr;
	idone:

//  ENABLE INSTRUCTION CACHE 

	p0.l = LO(IMEM_CONTROL); 
	p0.h = HI(IMEM_CONTROL);

	r0 = (IMC | ENICPLB);
	[p0] = r0;
	ssync;
#endif //(INSTR_CACHE_EN)

#ifdef DATA_CACHE_EN
	
//  INITIALIZE DATA CPLBs
	i0.l = lo(DCPLB_ADDR0);
	i0.h = hi(DCPLB_ADDR0);

	i1.l = lo(DCPLB_DATA0);
	i1.h = hi(DCPLB_DATA0);

	i2.l = dcplbs_table;
	i2.h = dcplbs_table;

	r1 = -1;  	// end point comparison 
	r3 = 15;  	// max counter 

	// read entries from table 
	read_daddr:
		r0 = [i2++];
		cc = r0 == r1;
		if cc jump ddone;
		[i0++] = r0;
	read_ddata:
		r2 = [i2++];
		[i1++] = r2;
		r3 = r3 + r1;
		cc = r3 == r1;
		if !cc jump read_daddr;
	ddone:

//  ENABLE DATA CPLBS
	p0.l = lo(DMEM_CONTROL);
	p0.h = hi(DMEM_CONTROL);

	// DCACHE_CONFIG is a #define in cache_init.h
	r0 = (DCACHE_CONFIG | ENDCPLB);
	[p0] = r0;
	ssync;
				
#endif //(DATA_CACHE_EN)


	rts;
cache_init.end:	



.section L1_data_a;
.align 4;

#ifdef DATA_CACHE_EN

#define SDRAM_DNON_CHBL  	(PAGE_SIZE_1MB | CPLB_SUPV_WR | CPLB_LOCK  | CPLB_VALID)
#define L1_DMEMORY			(PAGE_SIZE_1MB | CPLB_SUPV_WR | CPLB_LOCK  | CPLB_VALID)	

#ifdef DCACHE_WB
	#define SDRAM_DGENERIC	(PAGE_SIZE_1MB | CPLB_L1_CHBL | CPLB_DIRTY | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID)
#else
	#define SDRAM_DGENERIC	(PAGE_SIZE_1MB | CPLB_L1_CHBL | CPLB_WT | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID)
#endif // DCACHE_WB


	dcplbs_table:
	.byte4=
		0xFF800000, (L1_DMEMORY), 		//  DATA BANK A SRAM
		0xFF900000, (L1_DMEMORY),		//  DATA BANK B SRAM
		0x00000000, (SDRAM_DNON_CHBL),	//	SDRAM_Page0
		0x00100000, (SDRAM_DGENERIC),	//	SDRAM_Page1
		0x00200000, (SDRAM_DGENERIC),	//	SDRAM_Page2
		0x00300000, (SDRAM_DGENERIC),	//	SDRAM_Page3
		0xffffffff;	// end of section - termination	
#endif //(DATA_CACHE_EN)

#ifdef INSTR_CACHE_EN

	/************************************************************
	* 	Bit 9 of the ICPLB_DATAx is shown as Reserved bit		*
	*	however, when ICACHE is used this bit needs to be		*
	*	set to the same state as bit 12 (CPLB_L1_CHBL) 			*
	*	of this register as a workaround to anomaly: 05000258	*
	* 	This bit is defined in cache_init.h						*				
	************************************************************/
	#define SDRAM_IGENERIC		(PAGE_SIZE_1MB | CPLB_L1_CHBL | Bit9 | CPLB_USER_RD | CPLB_VALID)
	#define SDRAM_INON_CHBL  	(PAGE_SIZE_1MB | CPLB_USER_RD | CPLB_VALID)
	#define L1_IMEMORY			(PAGE_SIZE_1MB | CPLB_LOCK  | CPLB_VALID)	
	icplbs_table:
	.byte4=
		0xFFA00000, (L1_IMEMORY), 		//  L1 SRAM
		0x00000000, (SDRAM_INON_CHBL),	//	SDRAM_Page0
		0x00100000, (SDRAM_IGENERIC),	//	SDRAM_Page1
		0x00200000, (SDRAM_IGENERIC),	//	SDRAM_Page2
		0x00300000, (SDRAM_IGENERIC),	//	SDRAM_Page3
		0xffffffff;	// end of section - termination
#endif //(INSTR_CACHE_EN)

page_size_table:
.byte4=
	0x00000400,	/* 1K */
	0x00001000,	/* 4K */
	0x00100000,	/* 1M */
	0x00400000; /* 4M */