cache_init.h

基于visual dsp++开发环境

/* valid defines for instruction cache */
#define INSTR_CACHE_EN

/* valid defines for data cache */
#define DATA_CACHE_EN

/* choose 1 of the following 2 when data cache enabled */
#define DCACHE_CONFIG ACACHE_BSRAM
//#define DCACHE_CONFIG ACACHE_BCACHE

/* Default is Write-through.  */
//#define DCACHE_WB

/************************************************************
* 	Bit 9 of the ICPLB_DATAx is shown as Reserved bit		*
*	however, when ICACHE is used this bit needs to be		*
*	set to the same state as bit 12 (CPLB_L1_CHBL) 			*
*	of this register as a workaround to anomaly: 05000258	*		
*************************************************************/ 	
#define Bit9 0x0200