initialization.asm

基于visual dsp++开发环境

#include "Talkthrough.h"
/*****************************************************************************
 Function:	Init_Flags													
																		
 Description:	Configure PORTF flags to control ADC and DAC RESETs
 													
******************************************************************************/
.section L1_code;

Init_Flags:
	// configure programmable flags
	// set PORTF function enable register (need workaround)
	p0.l = lo(PORTF_FER);
    p0.h = hi(PORTF_FER);
    r0.l = 0x0000;
    r1 = w[p0] (z);
    ssync;
    w[p0] = r0;
    ssync;
    w[p0] = r0;
    ssync;

	// set PORTF direction register
    p0.l = lo(PORTFIO_DIR);
    p0.h = hi(PORTFIO_DIR);
    r0.l = 0x1FC0;
    w[p0] = r0;
    ssync; 
        
   	// set PORTF input enable register
    p0.l = lo(PORTFIO_INEN);
    p0.h = hi(PORTFIO_INEN);
    r0.l = 0x003C;
    w[p0] = r0;
    ssync; 
         
	// set PORTF clear register
    p0.l = lo(PORTFIO_CLEAR);
    p0.h = hi(PORTFIO_CLEAR);
    r0.l = 0x0FC0;
    w[p0] = r0;
    ssync;	
 
Init_Flags.END:
RTS;
/*****************************************************************************
 Function:	Audio_Reset
					
 Description:	This function Resets the ADC and DAC. 
		
******************************************************************************/   
Audio_Reset:
   
    // give some time for reset to take affect
    p2.l = lo(delay);
	p2.h = hi(delay);
	lsetup(delay_loop, delay_loop) lc0=p2;
	delay_loop: nop;	
	
    // set port f set register
    p0.l = lo(PORTFIO_SET);
    p0.h = hi(PORTFIO_SET);
    r0.l = PF12;
    w[p0] = r0;
    ssync;
    

Audio_Reset.END:
RTS;
/*****************************************************************************
 Function:	Init_Sport0													
																			
 Description:	Configure Sport0 for I2S mode, to transmit/receive data 
		to/from the ADC and DAC. 
		
******************************************************************************/
Init_Sport0:	
	
	// Sport0 receive configuration
	// External CLK, External Frame sync, MSB first, Active Low
	// 24-bit data, Secondary side enable, Stereo frame sync enable
	P0.L = LO(SPORT0_RCR1);
	P0.H = HI(SPORT0_RCR1);
//	R0 = RFSR | LRFS | RCKFE | IRFS | IRCLK;
	R0 = RFSR | LRFS | RCKFE;
	W[ P0 ] = R0.L;
	
	P0.L = LO(SPORT0_RCR2);
	P0.H = HI(SPORT0_RCR2);
	R0 = SLEN_24 | RXSE | RSFSE;
	W[ P0 ] = R0.L;

//	P0.L = LO(SPORT0_RCLKDIV);
//	P0.H = HI(SPORT0_RCLKDIV);
//	R0 = 0x13;
//	W[ P0 ] = R0.L;
	
//	P0.L = LO(SPORT0_RFSDIV);
//	P0.H = HI(SPORT0_RFSDIV);
//	R0 = 0x1F;
//	W[ P0 ] = R0.L;


	// Sport0 transmit configuration
	// External CLK, External Frame sync, MSB first, Active Low
	// 24-bit data, Secondary side enable, Stereo frame sync enable
	P0.L = LO(SPORT0_TCR1);
	P0.H = HI(SPORT0_TCR1);
	//R0 = TFSR | LTFS | TCKFE | ITFS | ITCLK;
	R0 = TFSR | LTFS | TCKFE;
	W[ P0 ] = R0.L;
	
	P0.L = LO(SPORT0_TCR2);
	P0.H = HI(SPORT0_TCR2);
	R0 = SLEN_24 | TXSE | TSFSE;
	W[ P0 ] = R0.L;
		
//	P0.L = LO(SPORT0_TCLKDIV);
//	P0.H = HI(SPORT0_TCLKDIV);
//	R0 = 0x13;
//	W[ P0 ] = R0.L;
	
//	P0.L = LO(SPORT0_TFSDIV);
//	P0.H = HI(SPORT0_TFSDIV);
//	R0 = 0x1F;
//	W[ P0 ] = R0.L;

Init_Sport0.END:
	RTS;
	
	
/*****************************************************************************
 Function:	Init_DMA												

 Description:	Initialize DMA3 in autobuffer mode to receive and DMA4 in	
				autobuffer mode to transmit									
******************************************************************************/
.section L1_code;
Init_DMA:
	
	// Configure DMA3
	// 32-bit transfers, Interrupt on completion, Autobuffer mode
	P1.L = LO(DMA3_CONFIG);
	P1.H = HI(DMA3_CONFIG);
	R1 = WNR | WDSIZE_32 | DI_EN | FLOW_1;	
	W[ P1 ] = R1.L; 
  	
	P2.H = rx_buf;
	P2.L = rx_buf;
	R1 = P2;
	
	// Start address of data buffer
	P1.L = LO(DMA3_START_ADDR);
	P1.H = HI(DMA3_START_ADDR);
	[ P1 ] = R1; 

	// DMA inner loop count
	P1.L = LO(DMA3_X_COUNT);
	P1.H = HI(DMA3_X_COUNT);
	R1.L = 4;	
	W[ P1 ] = R1.L; 

	// Inner loop address increment
	P1.L = LO(DMA3_X_MODIFY);
	P1.H = HI(DMA3_X_MODIFY);
	R1.L = 4;
	W[ P1 ] = R1.L; 
	
	// Configure DMA4
	// 32-bit transfers, Autobuffer mode
	P1.L = LO(DMA4_CONFIG);
	P1.H = HI(DMA4_CONFIG);
	R1 = WDSIZE_32 | FLOW_1;			
	W[ P1 ] = R1.L; 
  	
	P2.H = tx_buf;
	P2.L = tx_buf;
	R1 = P2;
	
	// Start address of data buffer
	P1.L = LO(DMA4_START_ADDR);
	P1.H = HI(DMA4_START_ADDR);
	[ P1 ] = R1; 

	// DMA inner loop count
	P1.L = LO(DMA4_X_COUNT);
	P1.H = HI(DMA4_X_COUNT);
	R1.L = 4;
	W[ P1 ] = R1.L; 

	// Inner loop address increment
	P1.L = LO(DMA4_X_MODIFY);
	P1.H = HI(DMA4_X_MODIFY);
	R1.L = 4;
	W[ P1 ] = R1.L; 

Init_DMA.END:
	RTS;

	
/*****************************************************************************
 Function:	Init_Interrupts												
																		
 Description:	Initialize Interrupt for Sport0 RX							
******************************************************************************/
.section L1_code;
Init_Interrupts:

	// Set Sport0 RX (DMA3) interrupt priority to 2 = IVG9 
	P0.L = LO(SIC_IAR0);
	P0.H = HI(SIC_IAR0);	
	R1.L = 0x0000;
	R1.H = 0x0020;
	[ P0 ] = R1;
	
	// Unmask peripheral SPORT0 RX interrupt
	P0.L = LO(SIC_IMASK);
	P0.H = HI(SIC_IMASK);
	R1 = [ P0 ];
	BITSET(R1, 5);
	[ P0 ] = R1;

	// Remap the vector table pointer from the default __I9HANDLER 
	// to the new _SPORT0_RX_ISR interrupt service routine
	P0.L = LO(EVT9);
	P0.H = HI(EVT9);
	R0.l = _SPORT0_RX_ISR;
	R0.h = _SPORT0_RX_ISR;
	[ P0 ] = R0;
	
	// Enable interrupts IVG9
	P0.L = LO(IMASK);
	P0.H = HI(IMASK);
	R7 = [ P0 ];
	R1.H = 0;
	R1.L = 0x0200;
	R7 = R7 | R1;
	[ P0 ] = R7;
	
Init_Interrupts.END:
	RTS;
	
/*****************************************************************************
 Function:	Enable_DMA_Sport											
																		
 Description:	Enable DMA3, DMA4, Sport0 TX and Sport0 RX					
******************************************************************************/
.section L1_code;
Enable_DMA_Sport0:

	// Enable DMA4
	P1.L = LO(DMA4_CONFIG);
	P1.H = HI(DMA4_CONFIG);
	R1.L = W[ P1 ];
	BITSET(R1,0);
	W[ P1 ] = R1.L; 

	// Enable DMA3
	P1.L = LO(DMA3_CONFIG);
	P1.H = HI(DMA3_CONFIG);
	R1.L = W[ P1 ];
	BITSET(R1,0);
	W[ P1 ] = R1.L; 
	
	// ENABLE SPORT0 TX
	P1.H = HI(SPORT0_TCR1);
	P1.L = LO(SPORT0_TCR1);
	R1.L = W[ P1 ];
	BITSET(R1,0);
	W[ P1 ] = R1; 

	// ENABLE SPORT0 RX
	P1.L = LO(SPORT0_RCR1);
	P1.H = HI(SPORT0_RCR1);
	R1.L = W[ P1 ];
	BITSET(R1,0);
	W[ P1 ] = R1; 
	
Enable_DMA_Sport0.END:
	RTS;