📄 blkfin16.frp
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PSDsoft Express Version 7.90
Output of PSD Fitter
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PROJECT : blkfin16 DATE : 09/15/2003
DEVICE : DSM2150F5V TIME : 11:30:43
FIT OPTION : Keep Current
DESCRIPTION: Reference design for ADSP-2153x BlackFin DSP and DSM2150F5.
16-bit mode. Connect Blackfin -ABE0, -ABE1, -ABE3, -AWE,
and -AOE to DSM inputs ADIO0, CNTL2, ADIO1, CNTL0, CNTL1 respectively.
Tie Blackfin A2 .. A15 to DSM ADIO2 .. ADIO1. Tie Sleep to PD2.
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==== Pin Layout for T (80-Pin TQFP) Package Type ====
-----------------------------
| |
sleep |1 ] pd2 pc0 [41| a16
pd3 |2 ] pd3 pc1 [42| a17
a0, Address Bus A0 |3 ] adio0 pc2 [43| a18
a1, Address Bus A1 |4 ] adio1 pc3 [44| a19
a2, Address Bus A2 |5 ] adio2 pc4 [45| a20
a3, Address Bus A3 |6 ] adio3 pc5 [46| a21
a4, Address Bus A4 |7 ] adio4 pc6 [47| _ams0
|8 ] GND pc7 [48| pc7
|9 ] VCC GND [49|
a5, Address Bus A5 |10] adio5 GND [50|
a6, Address Bus A6 |11] adio6 pa0 [51| pa0
a7, Address Bus A7 |12] adio7 pa1 [52| pa1
a8, Address Bus A8 |13] adio8 pa2 [53| pa2
a9, Address Bus A9 |14] adio9 pa3 [54| pa3
a10, Address Bus A10 |15] adio10 pa4 [55| pa4
a11, Address Bus A11 |16] adio11 pa5 [56| pa5
a12, Address Bus A12 |17] adio12 pa6 [57| pa6
a13, Address Bus A13 |18] adio13 pa7 [58| pa7
a14, Address Bus A14 |19] adio14 cntl0 [59| _awe
a15, Address Bus A15 |20] adio15 cntl1 [60| _aoe
d8 ,Data Port D8 |21] pg0 pb0 [61| pb0
d9 ,Data Port D9 |22] pg1 pb1 [62| pb1
d10 ,Data Port D10 |23] pg2 pb2 [63| pb2
d11 ,Data Port D11 |24] pg3 pb3 [64| pb3
d12 ,Data Port D12 |25] pg4 pb4 [65| pb4
d13 ,Data Port D13 |26] pg5 pb5 [66| pb5
d14 ,Data Port D14 |27] pg6 pb6 [67| pb6
d15 ,Data Port D15 |28] pg7 pb7 [68| pb7
|29] VCC VCC [69|
|30] GND GND [70|
d0 ,Data Port D0 |31] pf0 pe0/TMS [71| tms, TMS
d1 ,Data Port D1 |32] pf1 pe1/TCK [72| tck, TCK
d2 ,Data Port D2 |33] pf2 pe2/TDI [73| tdi, TDI
d3 ,Data Port D3 |34] pf3 pe3/TDO [74| tdo, TDO
d4 ,Data Port D4 |35] pf4 pe4/TSTAT [75| tstat, TSTAT
d5 ,Data Port D5 |36] pf5 pe5/TERR [76| _terr, TERR
d6 ,Data Port D6 |37] pf6 pe6 [77| pe6
d7 ,Data Port D7 |38] pf7 pe7 [78| pe7
_reset |39] reset pd0 [79| pd0
_abe1 |40] cntl2 pd1 [80| pd1
| |
-----------------------------
==== Global Configuration ====
Data Bus : 16-Bit
Address/Data Mode : Non-Multiplexed
ALE/AS Signal : Off
Control Signals : /WR, /RD, /BHE
Enable Chip-Select Input(/CSI) : ON
Standby Voltage Input (PE6) : OFF
Standby-on Indicator (PE7) : OFF
RDY/Busy function (PE4) : OFF
Security Protection : OFF
==== DataBus_IMC access information ====
CSIOP
Location Address Offset Register Name Signals
--------------------------------------------------------
===== Resource Usage Summary =====
Total Product Terms Used: 13
Device Resources used / total
------------------------------------------------
Port A: (pins 51 52 53 54 55 56 57 58)
I/O Pins : 8 / 8
MCU I/O : 8
Logic Inputs : 0
Address Latch Inputs : 0
PT Dependent Latch Inputs : 0
PT Dependent Register Inputs : 0
Combinatorial Outputs : 0
Registered Outputs : 0
Other Information
Microcells : 0 / 8
Micro-Cells A :
Buried Microcells : 0
Output Microcells : 0
Product Terms : 0 / 24
Control Product Terms : 0 / 34
Port B: (pins 61 62 63 64 65 66 67 68)
I/O Pins : 8 / 8
MCU I/O : 8
Logic Inputs : 0
Address Latch Inputs : 0
PT Dependent Latch Inputs : 0
PT Dependent Register Inputs : 0
Combinatorial Outputs : 0
Registered Outputs : 0
Other Information
Microcells : 0 / 8
Micro-Cells B :
Buried Microcells : 0
Output Microcells : 0
Product Terms : 0 / 32
Control Product Terms : 0 / 34
Port C: (pins 41 42 43 44 45 46 47 48)
I/O Pins : 8 / 8
MCU I/O : 1
Logic Inputs : 0
Address Latch Inputs : 7
PT Dependent Latch Inputs : 0
PT Dependent Register Inputs : 0
External Chip Selects : 0
Other Information
Product Terms : 0 / 8
Control Product Terms : 0 / 10
Port D: (pins 79 80 1 2)
I/O Pins : 4 / 4
MCU I/O : 3
Logic Inputs : 0
Control Signal Input : 0
Chip-Select Input : 1
Clock Input : 0
Port E: (pins 71 72 73 74 75 76 77 78)
I/O Pins : 8 / 8
MCU I/O or Address Out : 2
JTAG signals : 6
Standby Voltage Input : 0
Rdy/Bsy signal : 0
Standby On Indicator : 0
Port F: (pins 31 32 33 34 35 36 37 38)
I/O Pins : 8 / 8
MCU I/O or Address Out : 0
Peripheral I/O : 0
Logic Inputs : 0
External Chip Selects : 0
Data Port : 8
Other Information
Product Terms : 0 / 8
Control Product Terms : 0 / 8
Port G: (pins 21 22 23 24 25 26 27 28)
I/O Pins : 8 / 8
MCU I/O or Address Out : 0
Data Port : 8
==== OMC Resource Assignment ====
Resources PT User
Used Allocation Name
---------------------------------------------------------
Micro-Cell A :
Micro-Cell B :
External Chip Select :
========= Equations =========
DPLD EQUATIONS :
=======================
fs0 = !pdn & !_ams0 & !a21 & !a20 & !a19 & !a18 & a17 & !a16 & !sleep;
fs1 = !pdn & !_ams0 & !a21 & !a20 & !a19 & !a18 & a17 & a16 & !sleep;
fs2 = !pdn & !_ams0 & !a21 & !a20 & !a19 & a18 & !a17 & !a16 & !sleep;
fs3 = !pdn & !_ams0 & !a21 & !a20 & !a19 & a18 & !a17 & a16 & !sleep;
fs4 = !pdn & !_ams0 & !a21 & !a20 & !a19 & a18 & a17 & !a16 & !sleep;
fs5 = !pdn & !_ams0 & !a21 & !a20 & !a19 & a18 & a17 & a16 & !sleep;
fs6 = !pdn & !_ams0 & !a21 & !a20 & a19 & !a18 & !a17 & !a16 & !sleep;
fs7 = !pdn & !_ams0 & !a21 & !a20 & a19 & !a18 & !a17 & a16 & !sleep;
csboot0 = !pdn & !a15 & !a14 & !a13 & !_ams0 & !a21 & !a20 & !a19 & !a18 & !a17 & !a16 & !sleep;
csboot1 = !pdn & !a15 & !a14 & a13 & !_ams0 & !a21 & !a20 & !a19 & !a18 & !a17 & !a16 & !sleep;
csboot2 = !pdn & !a15 & a14 & !a13 & !_ams0 & !a21 & !a20 & !a19 & !a18 & !a17 & !a16 & !sleep;
csboot3 = !pdn & !a15 & a14 & a13 & !_ams0 & !a21 & !a20 & !a19 & !a18 & !a17 & !a16 & !sleep;
csiop = !pdn & !a15 & !a14 & !a13 & !a12 & !a11 & !a10 & !a9 & !a8 & !_ams0 & !a21 & !a20 & !a19 & !a18 & !a17 & a16 & !sleep;
PORTA EQUATIONS :
=======================
PORTB EQUATIONS :
=======================
PORTC EQUATIONS :
=======================
PORTF EQUATIONS :
=======================
--- End ---
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