fs7805regs.h

FS7805 使用DMA的demo

EXTERN xdata volatile BYTE I2C_CTL           _AT_ 0xFEC8;  // I2C Control Register
EXTERN xdata volatile BYTE I2C_CLK           _AT_ 0xFEC9;  // I2C Clock Control Register
EXTERN xdata volatile BYTE I2C_STUS          _AT_ 0xFECA;  // I2C Status Register
EXTERN xdata volatile BYTE I2C_SADDR         _AT_ 0xFECB;  // I2C Interrupt Enable Register
EXTERN xdata volatile BYTE I2C_DBUF          _AT_ 0xFECC;  // I2C Shift Data Transmit/Receive Buffer Register
EXTERN xdata volatile BYTE I2C_MABT          _AT_ 0xFECD;  // I2C Master Abort Time Out Register

EXTERN xdata volatile BYTE SFI_SKIP          _AT_ 0xFED0;  // Skip Packet to/from SFI
EXTERN xdata volatile BYTE SFI_FLGST         _AT_ 0xFED1;  // SFI Pin Flag Status Register
EXTERN xdata volatile BYTE PINFLAGAB         _AT_ 0xFED2;  // Slave FIFO Pin Flag AB Configuration
EXTERN xdata volatile BYTE PINFLAGC          _AT_ 0xFED3;  // Slave FIFO Pin Flag C Configuration
EXTERN xdata volatile BYTE SFI_DISABLE       _AT_ 0xFED4;  // Slave FIFO Interface Endpoint DISABLE Register
EXTERN xdata volatile BYTE SFI_EPCFG         _AT_ 0xFED5;  // Slave FIFO Endpoint Configuration Register
EXTERN xdata volatile BYTE SFI_EPAINLENL     _AT_ 0xFED6;  // Slave FIFO Endpoint A IN Packet Length Low-Byte Register
EXTERN xdata volatile BYTE SFI_EPABINLENH    _AT_ 0xFED7;  // Slave FIFO Endpoint AB IN Packet Length high Byte Register
EXTERN xdata volatile BYTE SFI_EPBINLENL     _AT_ 0xFED8;  // Slave FIFO Endpoint B IN Packet Length Low-Byte Register
EXTERN xdata volatile BYTE SFI_EPCINLENL     _AT_ 0xFED9;  // Slave FIFO Endpoint C IN Packet Length Low-Byte Register
EXTERN xdata volatile BYTE SFI_EPCDINLENH    _AT_ 0xFEDA;  // Slave FIFO Endpoint CD IN Packet Length high Byte Register
EXTERN xdata volatile BYTE SFI_EPDINLENL     _AT_ 0xFEDB;  // Slave FIFO Endpoint D IN Packet Length Low-Byte Register
EXTERN xdata volatile BYTE SFI_EPPFSTS       _AT_ 0xFEDC;  // Slave FIFO Endpoint Programmable-Level Full Status Register
EXTERN xdata volatile BYTE SFI_EPAPFTHREDL   _AT_ 0xFEDD;  // Slave FIFO Endpoint A Programmable-Level Full Threshold, Low Byte
EXTERN xdata volatile BYTE SFI_EPBPFTHREDL   _AT_ 0xFEDE;  // Slave FIFO Endpoint B Programmable-Level Full Threshold, Low Byte
EXTERN xdata volatile BYTE SFI_EPCPFTHREDL   _AT_ 0xFEDF;  // Slave FIFO Endpoint C Programmable-Level Full Threshold, Low Byte

EXTERN xdata volatile BYTE SFI_EPDPFTHREDL   _AT_ 0xFEE0;  // Slave FIFO Endpoint D Programmable-Level Full Threshold, Low Byte
EXTERN xdata volatile BYTE SFI_EPPFTHREDH    _AT_ 0xFEE1;  // Slave FIFO Endpoint Programmable-Level Full Threshold, High Byte
EXTERN xdata volatile BYTE SFI_EPINT         _AT_ 0xFEE2;  // Slave FIFO Endpoint Status Interrupts Register
EXTERN xdata volatile BYTE SFI_EPINTE        _AT_ 0xFEE3;  // Slave FIFO Endpoint Interrupts Enable Register

EXTERN xdata volatile BYTE ECC_CTL           _AT_ 0xFEE8;  // ECC control register
EXTERN xdata volatile BYTE ECC_RST           _AT_ 0xFEE9;  // ECC reset register
EXTERN xdata volatile BYTE ECC1_0            _AT_ 0xFEEA;  // ECC1 (bit 23:16)
EXTERN xdata volatile BYTE ECC1_1            _AT_ 0xFEEB;  // ECC1 (bit 15:8)
EXTERN xdata volatile BYTE ECC1_2            _AT_ 0xFEEC;  // ECC1 (bit 7:0)
EXTERN xdata volatile BYTE ECC2_0            _AT_ 0xFEED;  // ECC2 (bit 21:16)
EXTERN xdata volatile BYTE ECC2_1            _AT_ 0xFEEE;  // ECC2 (bit 15:8)
EXTERN xdata volatile BYTE ECC2_2            _AT_ 0xFEEF;  // ECC2 (bit 7:0)

EXTERN xdata volatile BYTE HWTRAP            _AT_ 0xFEF0;  // Hardware Trap Register
EXTERN xdata volatile BYTE HW_TPROBSEL       _AT_ 0xFEF1;  // Hardware Trap Probe Select Register
EXTERN xdata volatile BYTE TPROBSEL          _AT_ 0xFEF2;  // Probe select

EXTERN xdata volatile BYTE WAVEDATA0[32]     _AT_ 0xFF00;  // APLIF Waveform Descriptor 0 Data
EXTERN xdata volatile BYTE WAVEDATA1[32]     _AT_ 0xFF20;  // APLIF Waveform Descriptor 1 Data
EXTERN xdata volatile BYTE WAVEDATA2[32]     _AT_ 0xFF40;  // APLIF Waveform Descriptor 2 Data
EXTERN xdata volatile BYTE WAVEDATA3[32]     _AT_ 0xFF60;  // APLIF Waveform Descriptor 3 Data

EXTERN xdata volatile BYTE APLIFDM_CTL       _AT_ 0xFFD0;  // APLIF Duplex mode Control Register
EXTERN xdata volatile BYTE APLIFHOLDTIME     _AT_ 0xFFD1;  // APLIF Output Data Hold Time Control Register
EXTERN xdata volatile BYTE APLIFIDLECTL      _AT_ 0xFFD2;  // APLIF Output State in IDLE State Control Register
EXTERN xdata volatile BYTE APLIFIOCFG        _AT_ 0xFFD3;  // APLIF Output Drive Control Register
EXTERN xdata volatile BYTE APLIFARL          _AT_ 0xFFD4;  // APLIF Address, Low Byte
EXTERN xdata volatile BYTE APLIFARH          _AT_ 0xFFD5;  // APLIF Address, High Byte
EXTERN xdata volatile BYTE APLIFREADYCFG     _AT_ 0xFFD6;  // APLIF Ready Input Configuration
EXTERN xdata volatile BYTE APLIFREADYSTAT    _AT_ 0xFFD7;  // APLIF Ready Input Status
EXTERN xdata volatile BYTE APLIFTCD          _AT_ 0xFFD8;  // APLIF Transaction Count Divisor Register

EXTERN xdata volatile BYTE EPAPLIFFLGSEL     _AT_ 0xFFE0;  // Endpoint A, B, C, D APLIF Flag Select
EXTERN xdata volatile BYTE EPAPLIFSTOP       _AT_ 0xFFE1;  // Endpoint A, B, C, D APLIF Stop Transaction
EXTERN xdata volatile BYTE APLIFABORT        _AT_ 0xFFE2;  // Abort APLIF
EXTERN xdata volatile BYTE APLIFIE           _AT_ 0xFFE3;  // APLIF Interrupt Enable
EXTERN xdata volatile BYTE APLIFI            _AT_ 0xFFE4;  // APLIF Interrupt Request
EXTERN xdata volatile BYTE APLIFTCH          _AT_ 0xFFE5;  // APLIF Transaction Count Value, High Byte
EXTERN xdata volatile BYTE APLIFTCL          _AT_ 0xFFE6;  // APLIF Transaction Count Value, Low Byte
EXTERN xdata volatile BYTE EPAAPLIFTRIG      _AT_ 0xFFE7;  // Endpoint A APLIF Trigger
EXTERN xdata volatile BYTE EPBAPLIFTRIG      _AT_ 0xFFE8;  // Endpoint B APLIF Trigger
EXTERN xdata volatile BYTE EPCAPLIFTRIG      _AT_ 0xFFE9;  // Endpoint C APLIF Trigger
EXTERN xdata volatile BYTE EPDAPLIFTRIG      _AT_ 0xFFEA;  // Endpoint D APLIF Trigger
EXTERN xdata volatile BYTE APLIFWAVESEL      _AT_ 0xFFEB;  // Waveform Selector
EXTERN xdata volatile BYTE APLIFS_DAT_H      _AT_ 0xFFEC;  // Read/Write APLIF Data, High Byte
EXTERN xdata volatile BYTE APLIFS_DAT_L      _AT_ 0xFFED;  // Read/Write APLIF Data, Low Byte, No Trigger Transaction
EXTERN xdata volatile BYTE APLIFS_DATX_L     _AT_ 0xFFEE;  // Read/Write APLIF Data, Low Byte, and Trigger Transaction
EXTERN xdata volatile BYTE APLIFTS           _AT_ 0xFFEF;  // APLIF Transaction Status

EXTERN xdata volatile BYTE UDMACRCL          _AT_ 0xFFF0;  // UDMA CRC Low-Byte Register
EXTERN xdata volatile BYTE UDMACRCH          _AT_ 0xFFF1;  // UDMA CRC High-Byte Register
EXTERN xdata volatile BYTE UDMACRCQUALIFIER  _AT_ 0xFFF2;  // UDMA CRC Qualifier Register
EXTERN xdata volatile BYTE FSTAT             _AT_ 0xFFF3;  // Flow State Register
EXTERN xdata volatile BYTE FSLOGIC           _AT_ 0xFFF4;  // Flow State Ready Logic Function Register
EXTERN xdata volatile BYTE FSEQ0CTL          _AT_ 0xFFF5;  // Flow State Logic 0 CTL Output Register
EXTERN xdata volatile BYTE FSEQ1CTL          _AT_ 0xFFF6;  // Flow State Logic 1 CTL Output Register
EXTERN xdata volatile BYTE FSTB              _AT_ 0xFFF7;  // Flow State Strobe Register
EXTERN xdata volatile BYTE FSTBEDGE          _AT_ 0xFFF8;  // Flow State Strobe Edge Register
EXTERN xdata volatile BYTE FSTBHPERIOD       _AT_ 0xFFF9;  // Flow State Strobe Period Register
EXTERN xdata volatile BYTE FSHOLDON          _AT_ 0xFFFA;  // Flow State Hold-On Register



#undef EXTERN
#undef _AT_

#define UDMACRCL             UDMACRCL
#define UDMACRCH             UDMACRCH
#define UDMACRCQUAL          UDMACRCQUALIFIER
#define FLOWSTATE            FSTAT
#define FLOWLOGIC            FSLOGIC
#define FLOWEQ0CTL           FSEQ0CTL
#define FLOWEQ1CTL           FSEQ1CTL
#define FLOWSTB              FSTB
#define FLOWSTBEDGE          FSTBEDGE
#define FLOWSTBHPERIOD       FSTBHPERIOD
#define FLOWHOLDOFF          FSHOLDON
/*
*********************************************************************************************************
*                                          SPECIAL FUNCTION REGISTERS
*********************************************************************************************************
*/
sfr P0    = 0x80;                                          // Port 0
    sbit P0_7 = P0^7;
    sbit P0_6 = P0^6;
    sbit P0_5 = P0^5;
    sbit P0_4 = P0^4;
    sbit P0_3 = P0^3;
    sbit P0_2 = P0^2;
    sbit P0_1 = P0^1;
    sbit P0_0 = P0^0;
sfr SP    = 0x81;                                          // Stack Pointer
sfr DPL0  = 0x82;                                          // Data Pointer 2 Bytes, Low Byte
sfr DPH0  = 0x83;                                          // Data Pointer 2 Bytes, High Byte
sfr PCON  = 0x87;                                          // Power Control
    #define SMOD_       0x80
    #define GF1_        0x08
    #define GF0_        0x04
    #define PD_         0x02
    #define IDL_        0x01
sfr TCON  = 0x88;                                          // Timer/Counter Control
    sbit TF1  = TCON^7;
    sbit TR1  = TCON^6;
    sbit TF0  = TCON^5;
    sbit TR0  = TCON^4;
    sbit IE1  = TCON^3;
    sbit IT1  = TCON^2;
    sbit IE0  = TCON^1;
    sbit IT0  = TCON^0;
sfr TMOD  = 0x89;                                          // Timer/Counter Mode Control
    #define T1_GATE_    0x80
    #define T1_CT_      0x40
    #define T1_M1_      0x20
    #define T1_M0_      0x10
    #define T0_GATE_    0x08
    #define T0_CT_      0x04
    #define T0_M1_      0x02
    #define T0_M0_      0x01
sfr TL0   = 0x8A;                                          // Timer/Counter O Low Byte
sfr TL1   = 0x8B;                                          // Timer/Counter 1 Low Byte
sfr TH0   = 0x8C;                                          // Timer/Counter O High Byte
sfr TH1   = 0x8D;                                          // Timer/Counter 1 High Byte
sfr CKCON = 0x8E;                                          // Clock Control
sfr P1    = 0x90;                                          // Port 1
    sbit P1_7 = P1^7;
    sbit P1_6 = P1^6;
    sbit P1_5 = P1^5;
    sbit P1_4 = P1^4;
    sbit P1_3 = P1^3;
    sbit P1_2 = P1^2;
    sbit P1_1 = P1^1;
    sbit P1_0 = P1^0;
sfr EIF   = 0x91;                                          // External Interrupt Flag(s)
sfr WTST  = 0x92;                                          //
sfr DPX0  = 0x93;                                          //
sfr SCON0 = 0x98;                                          // Serial Control
    sbit SM00 = SCON0^7;
    sbit SM01 = SCON0^6;
    sbit SM02 = SCON0^5;
    sbit REN0 = SCON0^4;
    sbit TB08 = SCON0^3;
    sbit RB08 = SCON0^2;
    sbit TI0  = SCON0^1;
    sbit RI0  = SCON0^0;
sfr SBUF0 = 0x99;                                          // Serial Data Buffer
sfr P2    = 0xA0;                                          // Port 2
    sbit P2_7 = P2^7;
    sbit P2_6 = P2^6;
    sbit P2_5 = P2^5;
    sbit P2_4 = P2^4;
    sbit P2_3 = P2^3;
    sbit P2_2 = P2^2;
    sbit P2_1 = P2^1;
    sbit P2_0 = P2^0;
sfr IE    = 0xA8;                                          // Interrupt Enable Control
    sbit EA   = IE^7;
    sbit IE6  = IE^6;
    sbit IE5  = IE^5;
    sbit IE4  = IE^4;
    sbit IE3  = IE^3;
    sbit IE2  = IE^2;
    sbit ET0  = IE^1;