fs7805regs.h

FS7805 使用LED的demo FS7805 使用LED的demo

#define bmIDLE3MIE          bmBIT1                         // USB Bus Suspend Interrupt Enable
#define bmRESUMEIE          bmBIT2                         // USB Bus Resume Interrupt Enable
#define bmLIMITIE           bmBIT7                         // Error Count Limit interrupt Enable, high-active

// USB Endpoint 0 Receive Token Status Register(EP0RXTKN)
#define bmEP0_OUT           bmBIT0                         // RX OUT packet
#define bmEP0_SETUP         bmBIT1                         // RX SETUP packet
#define bmEP0_SETUPOW       bmBIT2                         // SETUP Overwrite

// USB Endpoint 0 Receive Command/Status Register(EP0RXCS)
#define bmRX0_EN            bmBIT0                         // RX Enable
#define bmRX0_SESTALL       bmBIT1                         // Send STALL
#define bmRX0_TOGGLE        bmBIT2                         // Data Toggle Bit
#define bmRX0_TOGERR        bmBIT3                         // Data Toggle Error
#define bmRX0_ACK           bmBIT4                         // ACK Status
#define bmRX0_STALL         bmBIT5                         // STALL Status
#define bmRX0_STSERR        bmBIT6                         // Error Status
#define bmRX0_CLRTOG        bmBIT7                         // Clear EP0 Data Toggle Bit

// USB Endpoint 0 Transmit Command/Status Register(EP0TXCS)
#define bmTX0_EN            bmBIT0                         // TX Enable
#define bmTX0_SESTALL       bmBIT1                         // Send STALL
#define bmTX0_TOGGLE        bmBIT2                         // Data Toggle Bit
#define bmTX0_ACK           bmBIT4                         // ACK Status
#define bmTX0_STALL         bmBIT5                         // STALL Status
#define bmTX0_STSERR        bmBIT6                         // Error Status
#define bmTX0_CLRTOG        bmBIT7                         // Clear EP0 Data Toggle Bit

// USB Endpoint A, B, C, D FIFO Configure Register(EPFIFOCFG)
#define bmEPA_FIFO_NUM      bmBIT0                         // EPA FIFO Number
#define bmEPA_FIFO_SIZE     bmBIT1                         // EPA FIFO Size
#define bmEPB_FIFO_NUM      bmBIT2                         // EPB FIFO Number
#define bmEPB_FIFO_SIZE     bmBIT3                         // EPB FIFO Size
#define bmEPC_FIFO_NUM      bmBIT4                         // EPC FIFO Number
#define bmEPC_FIFO_SIZE     bmBIT5                         // EPC FIFO Size
#define bmEPD_FIFO_NUM      bmBIT6                         // EPD FIFO Number
#define bmEPD_FIFO_SIZE     bmBIT7                         // EPD FIFO Size

// USB Endpoint A,B,C,D Control Register(EPACTRL/EPBCTRL/EPCCTRL/EPDCTRL)
#define bmEP_DIR            bmBIT2                         // Endpoint Direction
#define bmEP_EN             bmBIT3                         // Endpoint Enable/Disable

// USB Endpoint A,B,C,D Command/Status Register(EPACS/EPBCS/EPCCS/EPDCS)
#define bmEP_RXTXEN         bmBIT0                         // TX Enable, RX Enable
#define bmEP_SESTALL        bmBIT1                         // Send STALL
#define bmEP_TOG            bmBIT2                         // Data Toggle Bit
#define bmEP_TOGERR         bmBIT3                         // Data Toggle error
#define bmEP_ACK            bmBIT4                         // ACK Status
#define bmEP_STALL          bmBIT5                         // STALL Status
#define bmEP_STSERR         bmBIT6                         // Error Status
#define bmEP_CLRTOG         bmBIT7                         // Clear Data Toggle Bit

// Endpoint A,B,C,D Ping-Pong FIFO Count High-Byte Register(EPACNTH/EPBCNTH/EPCCNTH/EPDCNTH)
#define bmCNT0HWEN          bmBIT3                         // Write Enable of EP_CNT0[10:8]
#define bmCNT1HWEN          bmBIT7                         // Write Enable of EP_CNT0[10:8]

// USB Endpoint A,B,C,D FIFO Control/Status Register(EPAFIFOCS/EPBFIFOCS/EPCFIFOCS/EPDFIFOCS)
#define bmFIFO_TOG          bmBIT0                         // FIFO number for the current transaction
#define bmBULK_HEAP         bmBIT1                         // BULK Transfer Heap Enable
#define bmFIFO0_FULL        bmBIT2                         // FIFO0 full status
#define bmFIFO1_FULL        bmBIT3                         // FIFO1 full status
#define bmFIFO_TOG_WE       bmBIT4                         // Write Enable of FIFO_TOG
#define bmBULK_HEAP_WE      bmBIT5                         // Write Enable of BULK_HEAP
#define bmFIFO0_FULL_WE     bmBIT6                         // Write Enable of FIFO0_FULL
#define bmFIFO1_FULL_WE     bmBIT7                         // Write Enable of FIFO1_FULL

// USB PHY Test Mode Register(PHYTEST)
#define bmTEST_PKT          bmBIT0                         // SW sets this bit to 1 if the test selector is Test_Packet
#define bmTEST_SE0_NAK      bmBIT1                         // SW sets this bit to 1 if the test selector is Test_SE0_NAK
#define bmTEST_J            bmBIT2                         // SW sets this bit to 1 if the test selector is Test_J
#define bmTEST_K            bmBIT3                         // SW sets this bit to 1 if the test selector is Test_K

// SPI Control Register(SPI_CTL)
#define bmLSBF              bmBIT0                         // Low Significant Bit First
#define bmCPHA              bmBIT1                         // Clock Phase Bit
#define bmCPOL              bmBIT2                         // Clock Polarity Bit
#define bmMSTR              bmBIT3                         // SPI Master Bit
#define bmSSOE              bmBIT4                         // SS Port Output Enable

// SPI Status Register(SPI_ST)
#define bmRFFINT            bmBIT0                         // Receive Full Flag
#define bmTEFINT            bmBIT1                         // Transmit Empty Flag
#define bmMODFINT           bmBIT2                         // SPI Mode Fault Detection Flag
#define bmWCEF              bmBIT3                         // Write Collision Error Flag
#define bmROEF              bmBIT4                         // Slave Mode Receive Overflow Error Flag
#define bmSPIIE             bmBIT6                         // SPI Empty/Full Interrupt Enable
#define bmMODFIE            bmBIT7                         // SPI Mode Fault Detection Interrupt Enable

// I2C Control Register(I2C_CTL)
#define bmSTOP              bmBIT0                         // Stop condition generation bit
#define bmSTART             bmBIT1                         // Start Condition Generation bit
#define bmMST_MODE          bmBIT5                         // I2C bus master mode configure bit
#define bmI2CMODE           bmBIT6                         // I2C Bus Interface Mode Select

// I2C Status Register(I2C_STUS)
#define bmRX_DONE_INT       bmBIT0                         // Receive Done Interrupt
#define bmTX_DONE_INT       bmBIT1                         // Transmit Done Interrupt
#define bmSTOP_DET_INT      bmBIT2                         // STOP Bit Detected
#define bmXFER_ABT_INT      bmBIT3                         // Transfer Abort Interrupt
#define bmMST_LOST_ARB_INT  bmBIT4                         // Master loses arbitration interrupt
#define bmHI_SPEED_MODE     bmBIT5                         // The I2C Bus Current Transaction is in High-speed Mode
#define bmSLV_MODE          bmBIT6                         // I2C Slave Interface Detect the Mode Asked by Master
#define bmADDR_MATCH        bmBIT7                         // I2C Slave Address Detect Address Match

// Slave FIFO Interface Skip Packet Control Register(SFI_SKIP)
#define bmEPA               bmBIT0                         // Skip/Pass EPA Packet
#define bmEPB               bmBIT1                         // Skip/Pass EPB Packet
#define bmEPC               bmBIT2                         // Skip/Pass EPC Packet
#define bmEPD               bmBIT3                         // Skip/Pass EPD Packet
#define bmFIFOSEL           bmBIT6                         // Skip/Pass a Packet stored in which Ping-Pong FIFO
#define bmSKIP              bmBIT7                         // Skip a Packet stored in Ping-Pong FIFO

// Slave FIFO Interface Pin Flag Status Register(SFI_FLGST)
#define bmEPA_FF            bmBIT0                         // Pin Full Flag Status of Endpoint A
#define bmEPB_FF            bmBIT1                         // Pin Full Flag Status of Endpoint B
#define bmEPC_FF            bmBIT2                         // Pin Full Flag Status of Endpoint C
#define bmEPD_FF            bmBIT3                         // Pin Full Flag Status of Endpoint D
#define bmEPA_EF            bmBIT4                         // Pin Empty Flag Status of Endpoint A
#define bmEPB_EF            bmBIT5                         // Pin Empty Flag Status of Endpoint B
#define bmEPC_EF            bmBIT6                         // Pin Empty Flag Status of Endpoint C
#define bmEPD_EF            bmBIT7                         // Pin Empty Flag Status of Endpoint D

// Slave FIFO Interface DISABLE Register(SFI_DISABLE)
#define bmEPA               bmBIT0                         // Disable/enable SFI interface of EPA
#define bmEPB               bmBIT1                         // Disable/enable SFI interface of EPB
#define bmEPC               bmBIT2                         // Disable/enable SFI interface of EPC
#define bmEPD               bmBIT3                         // Disable/enable SFI interface of EPD
#define bmSFI_DISABLE       bmBIT7                         // Slave FIFO Interface Disable

// Slave FIFO Interface Endpoint Configuration Register(SFI_EPCFG)
#define bmDATBUS_MOD        bmBIT0                         // SFI/APLIF data bus mode
#define bmAUTO              bmBIT1                         // Slave FIFO Interface Auto or Manual mode
#define bmPF_EN             bmBIT2                         // Programmable-level Full Flag  Generate Enable
#define bmPFI_TRIGEDGE      bmBIT3                         // Programmable-level Full  Interrupt Trigger Edge
#define bmASYN              bmBIT4                         // External master access SFI mode
#define bmSERIAL            bmBIT5                         // KSoc Data Bus Work in Serial Mode
#define bmSWAP              bmBIT6                         // Swap high/low bits of byte/words

// SFI Endpoint Programmable-level Full Status Register(SFI_EPPFSTS)
#define bmEPAPF             bmBIT0                         // EPA Programmable-level Full Flag Status
#define bmEPBPF             bmBIT1                         // EPB Programmable-level Full Flag Status
#define bmEPCPF             bmBIT2                         // EPC Programmable-level Full Flag Status
#define bmEPDPF             bmBIT3                         // EPB Programmable-level Full Flag Status
#define bmEPAPF_WE          bmBIT4                         // Write Enable of EPAPF
#define bmEPBPF_WE          bmBIT5                         // Write Enable of EPBPF
#define bmEPCPF_WE          bmBIT6                         // Write Enable of EPCPF
#define bmEPDPF_WE          bmBIT7                         // Write Enable of EPDPF

// SFI Endpoint FIFO Status Interrupt Register(SFI_EPINT)
#define bmEPAFFINT          bmBIT0                         // Endpoint A Full/Empty Interrupt and Packet end interrupt
#define bmEPBFFINT          bmBIT1                         // Endpoint B Full/Empty Interrupt and Packet end interrupt
#define bmEPCFFINT          bmBIT2                         // Endpoint C Full/Empty Interrupt and Packet end interrupt
#define bmEPDFFINT          bmBIT3                         // Endpoint D Full/Empty Interrupt and Packet end interrupt
#define bmEPAPFINT          bmBIT4                         // Endpoint A Programmable Full  Interrupt
#define bmEPBPFINT          bmBIT5                         // Endpoint B Programmable Full  Interrupt
#define bmEPCPFINT          bmBIT6                         // Endpoint C Programmable Full  Interrupt
#define bmEPDPFINT          bmBIT7                         // Endpoint D Programmable Full  Interrupt

// SFI EP Interrupt Enable Register(SFI_EPINTE)
#define bmEPAFFINTE         bmBIT0                         // Corresponding Endpoint A Full Interrupt Enable
#define bmEPBFFINTE         bmBIT1                         // Corresponding Endpoint B Full Interrupt Enable
#define bmEPCFFINTE         bmBIT2                         // Corresponding Endpoint C Full Interrupt Enable
#define bmEPDFFINTE         bmBIT3                         // Corresponding Endpoint D Full Interrupt Enable
#define bmEPAPFINTE         bmBIT4                         // Corresponding Endpoint A Programmable Full Interrupt Enable
#define bmEPBPFINTE         bmBIT5                         // Corresponding Endpoint B Programmable Full Interrupt Enable
#define bmEPCPFINTE         bmBIT6                         // Corresponding Endpoint C Programmable Full Interrupt Enable
#define bmEPDPFINTE         bmBIT7                         // Corresponding Endpoint D Programmable Full Interrupt Enable

// ECC control register(ECC_CTL)
#define bmECCM              bmBIT0                         // ECC mode select

// Hardware Trap Register(HWTRAP)
#define bmTPROB_EN          bmBIT0                         // Probe Enable
#define bmHWCFG_NOCHIRP_FS  bmBIT1                         // FS No Chirp Enable
#define bmHWCFG_NOCHIRP     bmBIT2                         // HS No Chirp Enable
#define bmBIST_EN           bmBIT3                         // Build In Self Test Enable
#define bmMCU_MODEL_EN      bmBIT4                         // External MCU Model Enable
#define bmCODE_FROM_P1_EN   bmBIT5                         // Internal Program Code Input From Port1 Enable
#define bmNO_BT             bmBIT6                         // T5 start work without wait SBT and IBT finished
#define bmHALF_BT           bmBIT7                         // T5 start work without wait SBT and IBT entirely finished

// APLIF Duplex Mode Control Register(APLIFDM_CTL)
#define bmFULL_DUPLEX       bmBIT0                         // APLIF Full-Duplex Mode Enable
#define bmADDREXT           bmBIT1                         // APLIF Address Extend Mode
#define bmSTPEPSEL          bmBIT2                         // APLIF Stop Flag Endpoint Select
#define bmSTATE_OUTPUT      bmBIT3