fs7805regs.h

Falsh 读写的demo

#define bmTDES_RST          bmBIT5                         // Active High.  Reset TDES
#define bmSDMI_RST          bmBIT6                         // Active High.  Reset SDMI
#define bmI2C_RST           bmBIT7                         // Active High.  Reset I2C

// Port Remote Wakeup Enable Control Register(RMWEN)
#define bmRMWEN0            bmBIT0                         // Port 0 Remote-wakeup Enable
#define bmRMWEN1            bmBIT1                         // Port 1 Remote-wakeup Enable
#define bmRMWEN2            bmBIT2                         // Port 2 Remote-wakeup Enable
#define bmRMWEN3            bmBIT3                         // P3 Remote-wakeup Enable
#define bmRMWEN4            bmBIT4                         // P4 Remote-wakeup Enable
#define bmRMWEN5            bmBIT5                         // P5 Remote-wakeup Enable

// Port 0 Pull-up Control(P0PUCTL)
#define bmP00PUCTL          bmBIT0                         // P07-P00 Pull-up Control
#define bmP01PUCTL          bmBIT1                         // P07-P00 Pull-up Control
#define bmP02PUCTL          bmBIT2                         // P07-P00 Pull-up Control
#define bmP03PUCTL          bmBIT3                         // P07-P00 Pull-up Control
#define bmP04PUCTL          bmBIT4                         // P07-P00 Pull-up Control
#define bmP05PUCTL          bmBIT5                         // P07-P00 Pull-up Control
#define bmP06PUCTL          bmBIT6                         // P07-P00 Pull-up Control
#define bmP07PUCTL          bmBIT7                         // P07-P00 Pull-up Control

// Port 1 Pull-up Control(P1PUCTL)
#define bmP10PUCTL          bmBIT0                         // P17-P10 Pull-up Control
#define bmP11PUCTL          bmBIT1                         // P17-P10 Pull-up Control
#define bmP12PUCTL          bmBIT2                         // P17-P10 Pull-up Control
#define bmP13PUCTL          bmBIT3                         // P17-P10 Pull-up Control
#define bmP14PUCTL          bmBIT4                         // P17-P10 Pull-up Control
#define bmP15PUCTL          bmBIT5                         // P17-P10 Pull-up Control
#define bmP16PUCTL          bmBIT6                         // P17-P10 Pull-up Control
#define bmP17PUCTL          bmBIT7                         // P17-P10 Pull-up Control

// Port 2 Pull-up Control(P2PUCTL)
#define bmP20PUCTL          bmBIT0                         // P27-P20 Pull-up Control
#define bmP21PUCTL          bmBIT1                         // P27-P20 Pull-up Control
#define bmP22PUCTL          bmBIT2                         // P27-P20 Pull-up Control
#define bmP23PUCTL          bmBIT3                         // P27-P20 Pull-up Control
#define bmP24PUCTL          bmBIT4                         // P27-P20 Pull-up Control
#define bmP25PUCTL          bmBIT5                         // P27-P20 Pull-up Control
#define bmP26PUCTL          bmBIT6                         // P27-P20 Pull-up Control
#define bmP27PUCTL          bmBIT7                         // P27-P20 Pull-up Control

// Port 3 Pull-up Control(P3PUCTL)
#define bmP30PUCTL          bmBIT0                         // P37-P30 Pull-up Control
#define bmP31PUCTL          bmBIT1                         // P37-P30 Pull-up Control
#define bmP32PUCTL          bmBIT2                         // P37-P30 Pull-up Control
#define bmP33PUCTL          bmBIT3                         // P37-P30 Pull-up Control
#define bmP34PUCTL          bmBIT4                         // P37-P30 Pull-up Control
#define bmP35PUCTL          bmBIT5                         // P37-P30 Pull-up Control
#define bmP36PUCTL          bmBIT6                         // P37-P30 Pull-up Control
#define bmP37PUCTL          bmBIT7                         // P37-P30 Pull-up Control

// Port 4 Pull-up Control(P4PUCTL)
#define bmP40PUCTL          bmBIT0                         // P47-P40 Pull-up Control
#define bmP41PUCTL          bmBIT1                         // P47-P40 Pull-up Control
#define bmP42PUCTL          bmBIT2                         // P47-P40 Pull-up Control
#define bmP43PUCTL          bmBIT3                         // P47-P40 Pull-up Control
#define bmP44PUCTL          bmBIT4                         // P47-P40 Pull-up Control
#define bmP45PUCTL          bmBIT5                         // P47-P40 Pull-up Control
#define bmP46PUCTL          bmBIT6                         // P47-P40 Pull-up Control
#define bmP47PUCTL          bmBIT7                         // P47-P40 Pull-up Control

// Port 5 Pull-up Control(P5PUCTL)
#define bmP50PUCTL          bmBIT0                         // P57-P50 Pull-up Control
#define bmP51PUCTL          bmBIT1                         // P57-P50 Pull-up Control
#define bmP52PUCTL          bmBIT2                         // P57-P50 Pull-up Control
#define bmP53PUCTL          bmBIT3                         // P57-P50 Pull-up Control
#define bmP54PUCTL          bmBIT4                         // P57-P50 Pull-up Control
#define bmP55PUCTL          bmBIT5                         // P57-P50 Pull-up Control
#define bmP56PUCTL          bmBIT6                         // P57-P50 Pull-up Control
#define bmP57PUCTL          bmBIT7                         // P57-P50 Pull-up Control

// Bi-direction Pad Pull-up Control(BPPUCTL)
#define bmAPLIFRDYPUCTL     bmBIT0                         // APLIF_RDY0-5 Pad Pull-Up Control
#define bmDOCDEXROMSELPUCTL bmBIT1                         // EXROMSEL_N and Docd related Pad Pull-Up Control
#define bmXDATRDWRPUCTL     bmBIT2                         // XDATRDB and XDATWRB PadPull-Up Control
#define bmSPIPUCTL          bmBIT3                         // SPI Related Pad Pull-Up Control
#define bmT01PUCTL          bmBIT4                         // T0 and T1 Pad Pull-Up Control
#define bmXFIFOCLKPUCTL     bmBIT5                         // XFIFO_CLK Pad Pull-Up Control
#define bmXADDRPUCTL        bmBIT6                         // XADDR0-15 Pad Pull-Up Control
#define bmXDATAPUCTL        bmBIT7                         // XDATA0-15 Pad Pull-Up Control

 
//SDMI Reg Bit Map
//EXTERN xdata volatile BYTE SDMI_CTL        _AT_ 0xFE31;  // SDMI Control Register
#define bmSD_CLK_EN				bmBIT0                     //Disable SDMI clock
#define bmSD_CLK_SEL			bmBIT1                     //Select SDMI clock
#define bmSD_BUS_4BIT_EN   		bmBIT2                     //4bit mode
#define bmSD_BUS_8BIT_EN   		bmBIT3                     //8bit mode
#define bmSD_AUTO_CLK_EN		bmBIT4                     //Enable the auto-disable SD Card clock
#define bmSD_CLK_40				bmBIT5	                   //SDMI clock source frequency


//EXTERN xdata volatile BYTE SDMI_INT        _AT_ 0xFE37;  //SDMI Interrupt Register
#define bmSD_COMPLETE_INT		bmBIT0                     //SD Card Complete Interrupt
#define bmSD_STS_CHANGE_INT		bmBIT1                     //SD Card Status Change Interrupt
//EXTERN xdata volatile BYTE SDMI_ST         _AT_ 0xFE36;  //SDMI Status Register
#define bmSD_EXIST				bmBIT0                     //SD Card Status
#define bmSD_WR_PROTECT			bmBIT1                     //SD Card write protect status
#define bmSD_BUSY				bmBIT2                     //SD Card Busy
#define bmSD_CRC16_ERR			bmBIT6                     //SD CRC16 Error Status
#define bmSD_CRC7_ERR			bmBIT7                     //SD CRC7 Error Status


//EXTERN xdata volatile BYTE SD_INT_EN       _AT_ 0xFE38;  //SDMI Interrupt Enable Register
#define bmSD_COMPLETE_INT_EN		bmBIT0                 //SD Card Complete Interrupt Enable
#define bmSD_STS_CHANGE_INT_EN		bmBIT1                 //SD Card Status Change Interrupt Enable
                                                        
// DMA Control Register(DMA_CTL)
#define bmTDMA_START        bmBIT0                         //When SW sets this bit to HIGH, TDMA starts
#define bmDMA_START         bmBIT1                         //When SW sets this bit to HIGH, DMA starts to read/write access memories

// DMA Control 2 Register(DMA_CTL2)
#define bmCNFLICT_EN        bmBIT0                         //DMA can turn off CPU clock if external memory bus conflict occurs
// Pulse Width Modulation Control Register(PWM_CTL)
#define bmPWM0_EN		bmBIT0                             //PWM0 Enable
#define bmPWM1_EN		bmBIT1                             //PWM1 Enable


// Random Number Generator (RNG) Control Register(RNG_CTL)
#define bmFREE_MODE         bmBIT0                         //RNG MODE
#define bmRNG_START         bmBIT1                         //RNG START
#define bmOUTWIDTH_64       bmBIT2                         //Output Random Number Width

// RNG Interrupt Register(RNG_INT)
#define bmRNG_VALID         bmBIT0                         // RNG Valid Out
#define bmRNG_ERR           bmBIT1                         // RNG Error

// RNG Interrupt Enable Register(RNG_INTE)
#define bmRNG_VALID_EN      bmBIT1                         // RNG Valid Out Interrupt Mask
#define bmRNG_ERR_EN        bmBIT1                         // RNG Error Interrupt Mask

// Key Protect Unit (KPU) Control Register(KPU_CTL)
#define bmKEY_READY         bmBIT0                         // Keys ready
#define bmGEN_KEY           bmBIT1                         // Key Generation
#define bmKEY_VLD           bmBIT3                         // Key Valid
#define bmMCU_ACCESS        bmBIT4                         // EERPOM accessible by MCU.  High active
#define bmDATADR_MOD        bmBIT5                         // EEPROM Size Select

// TDES Control Register(TDES_CTL)
#define bmTDES_START        bmBIT1                         // SW sets this bit to start TDES operation
#define bmDES_SEL           bmBIT2                         // Selection bit for DES or TDES mode
#define bmDEC_SEL           bmBIT3                         // Selection bit for encryption or decryption
#define bmMAC_EN            bmBIT4                         // SW sets this bit if TDES is expected to generate 8-byte signature
#define bmCLR_DATA          bmBIT5                         // SW sets this bit to clear TDES_DATA registers


#define bmTDES_DES_START		bmBIT1                     // 
#define bmTDES_DES_SEL			bmBIT2                     //
#define bmTDES_DEC_EN			bmBIT3                     // 
#define bmTDES_MAC_EN			bmBIT4                     // 
#define bmTDES_CLR_DATA			bmBIT5                     // 

// USB General Control Register(USBGCTRL)
#define bmPLUG              bmBIT1                         // Plug USB Device
#define bmSUSPEND           bmBIT2                         // Suspend Enable
#define bmHS_DETECTED       bmBIT6                         // USB HS Detect Complete
#define bmSPEED             bmBIT7                         // USB Device Speed

// USB Endpoint Interrupt Register(EPINT)
#define bmRX0INT            bmBIT0                         // EP0 USB RX Event Interrupt
#define bmTX0INT            bmBIT1                         // EP0 USB TX Event Interrupt
#define bmIN0INT            bmBIT2                         // EP0 USB IN Token Event Interrupt
#define bmEPAINT            bmBIT3                         // EPA Interrupt
#define bmEPBINT            bmBIT4                         // EPB Interrupt
#define bmEPCINT            bmBIT5                         // EPC Interrupt
#define bmEPDINT            bmBIT6                         // EPD Interrupt
#define bmSOFINT            bmBIT7                         // SOF Interrupt

// USB Endpoint Interrupt Enable Register(EPIE)
#define bmRX0IE             bmBIT0                         // EP0 USB RX Event Interrupt Enable
#define bmTX0IE             bmBIT1                         // EP0 USB TX Event Interrupt Enable
#define bmIN0IE             bmBIT2                         // EP0 USB IN Token Event Interrupt Enable
#define bmEPAIE             bmBIT3                         // EPA Interrupt Enable
#define bmEPBIE             bmBIT4                         // EPB Interrupt Enable
#define bmEPCIE             bmBIT5                         // EPC Interrupt Enable
#define bmEPDIE             bmBIT6                         // EPD Interrupt Enable
#define bmSOFIE             bmBIT7                         // SOF Interrupt Enable

// USB State Interrupt Event Register(STINT)
#define bmUSBRSTINT         bmBIT0                         // USB Bus Reset Event Detected
#define bmIDLE3MSINT        bmBIT1                         // USB Bus Suspend 3ms Detected
#define bmRESUMEINT         bmBIT2                         // USB Bus Resume Detected
#define bmLIMITINT          bmBIT7                         // Error Count interrupt

// USB State Interrupt Enable Register(STIE)
#define bmUSBRSTIE          bmBIT0                         // USB Bus Reset Interrupt Enable