📄 fs7805regs.h
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sbit EX0 = IE^0;
sfr P3 = 0xB0; // Port 3
sbit P3_7 = P3^7;
sbit P3_6 = P3^6;
sbit P3_5 = P3^5;
sbit P3_4 = P3^4;
sbit P3_3 = P3^3;
sbit P3_2 = P3^2;
sbit P3_1 = P3^1;
sbit P3_0 = P3^0;
sfr IP = 0xB8; // Interrupt Priority Control
sbit IP7 = IP^7;
sbit IP6 = IP^6;
sbit IP5 = IP^5;
sbit IP4 = IP^4;
sbit IP3 = IP^3;
sbit IP2 = IP^2;
sbit IP1 = IP^1;
sbit IP0 = IP^0;
sfr PSW = 0xD0; // Program Status Word
sbit CY = PSW^7;
sbit AC = PSW^6;
sbit F0 = PSW^5;
sbit RS1 = PSW^4;
sbit RS0 = PSW^3;
sbit OV = PSW^2;
sbit P = PSW^0;
sfr ACC = 0xE0; // Accumulator
sfr EIE = 0xE8; // External Interrupt Enable(s)
sfr MXAX = 0xEA; //
sfr TA = 0xEB; //
sfr SPCR = 0xEC; //
sfr SPSR = 0xED; //
sfr SPDR = 0xEE; //
sfr SSCR = 0xEF; //
sfr B = 0xF0; // B Register
sfr EIP = 0xF8; // External Interrupt Priority Control
/*
*********************************************************************************************************
* BIT MASKS
*********************************************************************************************************
*/
//EXTERN xdata volatile BYTE CHIPINT _AT_ 0xFE03; // Chip Interrupt Register
#define bmDMA_INT bmBIT0 // DMA Interrupt Event Enable
#define bmTDES_INT bmBIT1 // TDES Interrupt Event Enable
#define bmRNG_INT bmBIT2 // RNG Interrupt Event Enable
#define bmSPI_INT bmBIT3 // SPI Interrupt Event Enable
#define bmSDMI_INT bmBIT4 // SDMI Interrupt Event Enable
#define bmI2C_INT bmBIT5 // I2C Interrupt Event Enable
#define bmWDT_INT bmBIT6 // WDT Interrupt Event Enable
//EXTERN xdata volatile BYTE CHIPINTE _AT_ 0xFE04; // Chip Interrupt Mask Register
#define bmDMA_INT_EN bmBIT0 // DMA Interrupt Event Enable
#define bmTDES_INT_EN bmBIT1 // TDES Interrupt Event Enable
#define bmRNG_INT_EN bmBIT2 // RNG Interrupt Event Enable
#define bmSPI_INT_EN bmBIT3 // SPI Interrupt Event Enable
#define bmSDMI_INT_EN bmBIT4 // SDMI Interrupt Event Enable
#define bmI2C_INT_EN bmBIT5 // I2C Interrupt Event Enable
#define bmWDT_INT_EN bmBIT6 // WDT Interrupt Event Enable
// System Configuration Register(SYS_CFG)
#define bmIFCLKPOL bmBIT2 // Pin XFIFO_CLK Clock Polarity
#define bmCPUCLKOE bmBIT3 // Output enable for the internal CPU clock source
#define bmEXCLK_EN bmBIT4 // External Master Clock as KSOC Clock
#define bmSYS_SWRST bmBIT5 // Active High. Reset the whole chip
#define bmPM_AVBLE bmBIT6 // Internal Program Memory Available
#define bmBYPASSPLL bmBIT7 // Bypass PLL clock
//EXTERN xdata volatile BYTE SYS_CFG _AT_ 0xFE05; // System Configuration Register
#define bmCPUCLK_SEL bmBIT0|bmBIT1
#define bmIF_CLK_POL bmBIT2 //
#define bmCPU_CLK_OE bmBIT3 //
#define bmEX_CLK_EN bmBIT4 //
#define bmSYS_SW_RST bmBIT5 //
#define bmPM_AVBLE bmBIT6 //
#define bmBYPASS_PLL bmBIT7 //
// System IO Configuration Register(SYSIO_CFG)
//EXTERN xdata volatile BYTE SYSIO_CFG _AT_ 0xFE06; // System IO Configuration Register
#define bmSD_EN bmBIT2 // SD Card Function Enable
#define bmSPI_EN bmBIT3 // SPI Function Enable
#define bmI2C_EN bmBIT4 // I2C Function Enable
#define bmUART_EN bmBIT5 // UART Function Enable
#define bmEX_INT_EN bmBIT6 // INT0, INT1 Function Enable
// P0 Alternate Configuration Register(P0CFG)
#define bmAPLIFAI0_EN bmBIT0 // Enable APLIF Address IN Pins
#define bmAPLIFAI1_EN bmBIT1 // Enable APLIF Address IN Pins
#define bmAPLIFAI2_EN bmBIT2 // Enable APLIF Address IN Pins
#define bmAPLIFAI3_EN bmBIT3 // Enable APLIF Address IN Pins
#define bmAPLIFAI4_EN bmBIT4 // Enable APLIF Address IN Pins
#define bmAPLIFAI5_EN bmBIT5 // Enable APLIF Address IN Pins
#define bmAPLIFAI6_EN bmBIT6 // Enable APLIF Address IN Pins
#define bmAPLIFAI7_EN bmBIT7 // Enable APLIF Address IN Pins
// P3 Alternate Configuration Register(P3CFG)
#define bmAPLIFA0_EN bmBIT0 // Enable APLIF Address Pins
#define bmAPLIFA1_EN bmBIT1 // Enable APLIF Address Pins
#define bmAPLIFA2_EN bmBIT2 // Enable APLIF Address Pins
#define bmAPLIFA3_EN bmBIT3 // Enable APLIF Address Pins
#define bmAPLIFA4_EN bmBIT4 // Enable APLIF Address Pins
#define bmAPLIFA5_EN bmBIT5 // Enable APLIF Address Pins
#define bmAPLIFA6_EN bmBIT6 // Enable APLIF Address Pins
#define bmAPLIFA7_EN bmBIT7 // Enable APLIF Address Pins
// P0,P1,P2,P3,P4,P5 Output Enable(P0OE/P1OE/P2OE/P3OE/P4OE/P5OE)
#define bmP00_OE bmBIT0 // Output Enable of P0
#define bmP01_OE bmBIT1 // Output Enable of P0
#define bmP02_OE bmBIT2 // Output Enable of P0
#define bmP03_OE bmBIT3 // Output Enable of P0
#define bmP04_OE bmBIT4 // Output Enable of P0
#define bmP05_OE bmBIT5 // Output Enable of P0
#define bmP06_OE bmBIT6 // Output Enable of P0
#define bmP07_OE bmBIT7 // Output Enable of P0
// P1 Output Enable(P1OE)
#define bmP10_OE bmBIT0 // Output Enable of P1
#define bmP11_OE bmBIT1 // Output Enable of P1
#define bmP12_OE bmBIT2 // Output Enable of P1
#define bmP13_OE bmBIT3 // Output Enable of P1
#define bmP14_OE bmBIT4 // Output Enable of P1
#define bmP15_OE bmBIT5 // Output Enable of P1
#define bmP16_OE bmBIT6 // Output Enable of P1
#define bmP17_OE bmBIT7 // Output Enable of P1
// P2 Output Enable(P2OE)
#define bmP20_OE bmBIT0 // Output Enable of P2
#define bmP21_OE bmBIT1 // Output Enable of P2
#define bmP22_OE bmBIT2 // Output Enable of P2
#define bmP23_OE bmBIT3 // Output Enable of P2
#define bmP24_OE bmBIT4 // Output Enable of P2
#define bmP25_OE bmBIT5 // Output Enable of P2
#define bmP26_OE bmBIT6 // Output Enable of P2
#define bmP27_OE bmBIT7 // Output Enable of P2
// P3 Output Enable(P3OE)
#define bmP30_OE bmBIT0 // Output Enable of P3
#define bmP31_OE bmBIT1 // Output Enable of P3
#define bmP32_OE bmBIT2 // Output Enable of P3
#define bmP33_OE bmBIT3 // Output Enable of P3
#define bmP34_OE bmBIT4 // Output Enable of P3
#define bmP35_OE bmBIT5 // Output Enable of P3
#define bmP36_OE bmBIT6 // Output Enable of P3
#define bmP37_OE bmBIT7 // Output Enable of P3
// P4 Output Enable(P4OE)
#define bmP40_OE bmBIT0 // Output Enable of P4
#define bmP41_OE bmBIT1 // Output Enable of P4
#define bmP42_OE bmBIT2 // Output Enable of P4
#define bmP43_OE bmBIT3 // Output Enable of P4
#define bmP44_OE bmBIT4 // Output Enable of P4
#define bmP45_OE bmBIT5 // Output Enable of P4
#define bmP46_OE bmBIT6 // Output Enable of P4
#define bmP47_OE bmBIT7 // Output Enable of P4
// P5 Output Enable(P5OE)
#define bmP50_OE bmBIT0 // Output Enable of P5
#define bmP51_OE bmBIT1 // Output Enable of P5
#define bmP52_OE bmBIT2 // Output Enable of P5
#define bmP53_OE bmBIT3 // Output Enable of P5
#define bmP54_OE bmBIT4 // Output Enable of P5
#define bmP55_OE bmBIT5 // Output Enable of P5
#define bmP56_OE bmBIT6 // Output Enable of P5
#define bmP57_OE bmBIT7 // Output Enable of P5
// Port Direction Control(PDCTL)
#define bmP0D_CTL bmBIT0 // Port0 direction control
#define bmP1D_CTL bmBIT1 // Port1 direction control
#define bmP2D_CTL bmBIT2 // Port2 direction control
#define bmP3D_CTL bmBIT3 // Port3 direction control
#define bmP4D_CTL bmBIT4 // Port4 direction control
#define bmP5D_CTL bmBIT5 // Port5 direction control
#define bmOTHER_BDP_SUS_OE bmBIT6 // Other Bi-direction pad output enable during suspend
#define bmXDATA_SUS_OE bmBIT7 // XDATA[7:0] output enable during suspend
// DIT Function Configure and BOOT Result(TEST)
#define bmSTAND8051 bmBIT5 // External Target is Standard 8051. Active-high
// Software Reset Control Register(SW_RST)
#define bmUSB_RST bmBIT0 // Software USB Reset
#define bmSFI_RST bmBIT1 // SFI software reset
#define bmAPLIF_RST bmBIT2 // APLIF SW Reset
#define bmSPI_RST bmBIT3 // SPI SW Reset
#define bmDMA_RST bmBIT4 // DMA SW Reset
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