📄 sm.lst
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C51 COMPILER V7.50 SM 04/17/2007 10:39:20 PAGE 1
C51 COMPILER V7.50, COMPILATION OF MODULE SM
OBJECT MODULE PLACED IN .\Output\Sm.obj
COMPILER INVOKED BY: C:\Keil\C51\BIN\C51.EXE Sm.c LARGE OPTIMIZE(SIZE) BROWSE INCDIR(.\Include) DEBUG OBJECTEXTEND PRINT
-(.\Output\Sm.lst) OBJECT(.\Output\Sm.obj)
line level source
1 /*
2 *********************************************************************************************************
3 * File : Sm.C
4 * Contents :
5 *
6 * $Date : 09/18/06 Kimi v0.1
7 * $Date : 10/18/06 Kimi v0.2
8 * $Date : 11/02/06 Kimi v1.0
9 *
10 * Copyright (c) 2006 Fameg, Inc. All rights reserved
11 *********************************************************************************************************
12 */
13
14 #include "sm.h"
15
16 //----------------------------------------------------------------------------
17 // Description:
18 // Set SegmentBase
19 //----------------------------------------------------------------------------
20 void SmEraseAll (void)
21 {
22 1 UINT16 j;
23 1 UINT16 SmTotalBlocks = ((UINT16)1 << SmBlocksPerChipShift) * SmMaxChipsPerDevice;
24 1
25 1 for (j = 0; j < SmTotalBlocks; j++)
26 1 SmEraseBlock(j);
27 1 }
28
29 //----------------------------------------------------------------------------
30 // Description:
31 // Set SegmentBase
32 //----------------------------------------------------------------------------
33 void SmSetSegmentBase (BYTE Segment)
34 {
35 1 SegmentBase = (((UINT16)(Segment / PLANE_NUMBER) << SmBlock2SegShift) * PLANE_NUMBER) + (Segment % PLA
-NE_NUMBER);
36 1 }
37
38 //----------------------------------------------------------------------------
39 // Description:
40 // Parse the active FLASH chip Status
41 //----------------------------------------------------------------------------
42 STATUS SmParseStatus (STATUS Status)
43 {
44 1 if ((Status & 0x40) == 0)
45 1 {
46 2 return STATUS_FLASH_ERROR;
47 2 }
48 1 else if ((Status & 0x80) == 0)
49 1 {
50 2 return STATUS_WRITE_PROTECT;
51 2 }
52 1 else if ((Status & 0x01) == 1)
53 1 {
C51 COMPILER V7.50 SM 04/17/2007 10:39:20 PAGE 2
54 2 return STATUS_FLASH_ERROR;
55 2 }
56 1 else
57 1 {
58 2 return STATUS_SUCCESS;
59 2 }
60 1 }
61
62 //----------------------------------------------------------------------------
63 // Description:
64 // Select the active FLASH chip
65 //----------------------------------------------------------------------------
66 void SmSelectChip (BYTE Chip)
67 {
68 1 switch (Chip)
69 1 {
70 2 case 0:
71 2 APLIFARL = 0xFC;
72 2 ReadyBusy = 0x02;
73 2 break;
74 2 case 1:
75 2 APLIFARL = 0xFA;
76 2 ReadyBusy = 0x04;
77 2 break;
78 2 case 2:
79 2 APLIFARL = 0xF6;
80 2 ReadyBusy = 0x08;
81 2 break;
82 2 case 3:
83 2 APLIFARL = 0xEE;
84 2 ReadyBusy = 0x10;
85 2 break;
86 2 default:
87 2 ;
88 2 }
89 1 }
90
91 //----------------------------------------------------------------------------
92 // Description:
93 // Set the extra area of one block, especially the block address
94 //----------------------------------------------------------------------------
95 void SmSetBlockExtra (UINT16 BlockAddr)
96 {
97 1 BlockAddr &= SmBlockSegMask; // Segment LBA between 0 and 999
98 1 // Block Address Field = (Segment LBA) * 2 + 0x1000 + P (P : EvenParityData)
99 1 BlockAddr <<= 1;
100 1 BlockAddr |= 0x1000;
101 1 if (!EvenParity(BlockAddr))
102 1 {
103 2 BlockAddr |= 0x0001;
104 2 }
105 1
106 1 SpareArea[BLOCK_STS] = VALID_BLOCK;
107 1 SpareArea[DATA_STS] = VALID_DATA;
108 1
109 1 SpareArea[BLOCK_ADDR1_L] = ((TDataCast *)&BlockAddr)->ucByte[1];
110 1 SpareArea[BLOCK_ADDR2_L] = ((TDataCast *)&BlockAddr)->ucByte[1];
111 1 SpareArea[BLOCK_ADDR1_H] = ((TDataCast *)&BlockAddr)->ucByte[0];
112 1 SpareArea[BLOCK_ADDR2_H] = ((TDataCast *)&BlockAddr)->ucByte[0];
113 1 }
114
115 //----------------------------------------------------------------------------
C51 COMPILER V7.50 SM 04/17/2007 10:39:20 PAGE 3
116 // Description:
117 // Set the FLASH address for the followed FLASH access
118 //----------------------------------------------------------------------------
119 void SmSetFlashAddr (UINT32 Page)
120 {
121 1 BYTE Chip = Page >> SmPagesPerChipShift; // Calculate Chip Number
122 1 Page = Page & SmChipPageMask; // Make Chip Address in the correct range
123 1
124 1 SmSelectChip(Chip); // Select Corresponding Chip
125 1
126 1 FlashAddress[FLASH_ADDR0] = 0x00;
127 1 FlashAddress[FLASH_ADDR1] = 0x00;
128 1 FlashAddress[FLASH_ADDR2] = ((TDataCast *)&Page)->ucByte[3];
129 1 FlashAddress[FLASH_ADDR3] = ((TDataCast *)&Page)->ucByte[2];
130 1 FlashAddress[FLASH_ADDR4] = ((TDataCast *)&Page)->ucByte[1];
131 1 }
132
133 //----------------------------------------------------------------------------
134 // Description:
135 // Complete the NAND FLASH Command Function (Key Function)
136 //----------------------------------------------------------------------------
137 STATUS SmFlashCmd (BYTE Cmd)
138 {
139 1 switch (Cmd)
140 1 {
141 2 case FLASH_READ_EX:
142 2 FlashAddress[FLASH_ADDR1] = 0x08;
143 2 NanD_Command(0x00);
144 2 NanD_Address(FlashAddress[FLASH_ADDR0]);
145 2 NanD_Address(FlashAddress[FLASH_ADDR1]);
146 2 NanD_Address(FlashAddress[FLASH_ADDR2]);
147 2 NanD_Address(FlashAddress[FLASH_ADDR3]);
148 2 NanD_Address(FlashAddress[FLASH_ADDR4]);
149 2 NanD_Command(0x30);
150 2 while (!(APLIFREADYSTAT & ReadyBusy));
151 2 Nand_ReadSpare();
152 2 break;
153 2 case FLASH_READ:
154 2 NanD_Command(0x00);
155 2 NanD_Address(FlashAddress[FLASH_ADDR0]);
156 2 NanD_Address(FlashAddress[FLASH_ADDR1]);
157 2 NanD_Address(FlashAddress[FLASH_ADDR2]);
158 2 NanD_Address(FlashAddress[FLASH_ADDR3]);
159 2 NanD_Address(FlashAddress[FLASH_ADDR4]);
160 2 NanD_Command(0x30);
161 2 while (!(APLIFREADYSTAT & ReadyBusy));
162 2 Nand_ReadSector();
163 2 break;
164 2 case FLASH_READ_NEXT_DATA:
165 2 Nand_ReadSector();
166 2 break;
167 2 case FLASH_READ_ID:
168 2 NanD_Command(0x90);
169 2 NanD_Address(0x00);
170 2 FlashId[0] = NanD_Read();
171 2 FlashId[1] = NanD_Read();
172 2 FlashId[2] = NanD_Read();
173 2 FlashId[3] = NanD_Read();
174 2 FlashId[4] = NanD_Read();
175 2 break;
176 2 case FLASH_READ_STS:
177 2 NanD_Command(0x70);
C51 COMPILER V7.50 SM 04/17/2007 10:39:20 PAGE 4
178 2 FlashSts = NanD_Read();
179 2 break;
180 2 case FLASH_PROG:
181 2 NanD_Command(0x80);
182 2 NanD_Address(FlashAddress[FLASH_ADDR0]);
183 2 NanD_Address(FlashAddress[FLASH_ADDR1]);
184 2 NanD_Address(FlashAddress[FLASH_ADDR2]);
185 2 NanD_Address(FlashAddress[FLASH_ADDR3]);
186 2 NanD_Address(FlashAddress[FLASH_ADDR4]);
187 2 Nand_WriteSector();
188 2 break;
189 2 case FLASH_PROG_NEXT_DATA:
190 2 Nand_WriteSector();
191 2 break;
192 2 case FLASH_PROG_EX:
193 2 Nand_WriteSpare();
194 2 NanD_Command(0x10);
195 2 while (!(APLIFREADYSTAT & ReadyBusy));
196 2 break;
197 2 case FLASH_PAD:
198 2 FlashAddress[FLASH_ADDR1] = 0x08;
199 2 NanD_Command(0x80);
200 2 NanD_Address(FlashAddress[FLASH_ADDR0]);
201 2 NanD_Address(FlashAddress[FLASH_ADDR1]);
202 2 NanD_Address(FlashAddress[FLASH_ADDR2]);
203 2 NanD_Address(FlashAddress[FLASH_ADDR3]);
204 2 NanD_Address(FlashAddress[FLASH_ADDR4]);
205 2 Nand_WriteSpare();
206 2 NanD_Command(0x10);
207 2 while (!(APLIFREADYSTAT & ReadyBusy));
208 2 break;
209 2 case FLASH_ERASE:
210 2 NanD_Command(0x60);
211 2 NanD_Address(FlashAddress[FLASH_ADDR2]);
212 2 NanD_Address(FlashAddress[FLASH_ADDR3]);
213 2 NanD_Address(FlashAddress[FLASH_ADDR4]);
214 2 NanD_Command(0xD0);
215 2 while (!(APLIFREADYSTAT & ReadyBusy));
216 2 break;
217 2 case FLASH_CP:
218 2 NanD_Command(0x00);
219 2 NanD_Address(FlashAddress[FLASH_ADDR0]);
220 2 NanD_Address(FlashAddress[FLASH_ADDR1]);
221 2 NanD_Address(FlashAddress[FLASH_ADDR2]);
222 2 NanD_Address(FlashAddress[FLASH_ADDR3]);
223 2 NanD_Address(FlashAddress[FLASH_ADDR4]);
224 2 NanD_Command(0x35);
225 2 while (!(APLIFREADYSTAT & ReadyBusy));
226 2 break;
227 2 case FLASH_CP_PROG:
228 2 NanD_Command(0x85);
229 2 NanD_Address(FlashAddress[FLASH_ADDR0]);
230 2 NanD_Address(FlashAddress[FLASH_ADDR1]);
231 2 NanD_Address(FlashAddress[FLASH_ADDR2]);
232 2 NanD_Address(FlashAddress[FLASH_ADDR3]);
233 2 NanD_Address(FlashAddress[FLASH_ADDR4]);
234 2 NanD_Command(0x10);
235 2 while (!(APLIFREADYSTAT & ReadyBusy));
236 2 break;
237 2 default:
238 2 ;
239 2 }
C51 COMPILER V7.50 SM 04/17/2007 10:39:20 PAGE 5
240 1 SmCmdStatus = STATUS_SUCCESS;
241 1
242 1 return STATUS_SUCCESS;
243 1 }
244
245 //----------------------------------------------------------------------------
246 // Description:
247 // Read the FLASH ID and Quantity
248 //----------------------------------------------------------------------------
249 BYTE SmReadId (void)
250 {
251 1 BYTE RetryCount, Id[4], Chip;
252 1
253 1 for (Chip = 0; Chip < 4; Chip++) // Scan All Possible Chip
254 1 {
255 2 SmSelectChip(Chip); // Select Current Chip
256 2
257 2 for (RetryCount = 0; RetryCount < 3; RetryCount++)
258 2 {
259 3 if (SmFlashCmd(FLASH_READ_ID) != STATUS_SUCCESS)
260 3 {
261 4 continue;
262 4 }
263 3 Id[Chip] = FlashId[1];
264 3 break;
265 3 }
266 2 if (Id[0] != 0xFF)
267 2 {
268 3 if (Chip == 0)
269 3 {
270 4 SmMaxChipsPerDevice = 1;
271 4 }
272 3 else if (Id[Chip] == Id[0])
273 3 {
274 4 SmMaxChipsPerDevice++;
275 4 }
276 3 }
277 2 }
278 1 return Id[0];
279 1 }
280
281 //----------------------------------------------------------------------------
282 // Description:
283 // Read the FLASH status of Current Chip
284 //----------------------------------------------------------------------------
285 BYTE SmReadStatus (void)
286 {
287 1 BYTE RetryCount, Status;
288 1
289 1 for (RetryCount = 0; RetryCount < 3; RetryCount++)
290 1 {
291 2 if (SmFlashCmd(FLASH_READ_STS) != STATUS_SUCCESS)
292 2 {
293 3 continue;
294 3 }
295 2
296 2 Status = FlashSts;
297 2 break;
298 2 }
299 1 return Status;
300 1 }
301
C51 COMPILER V7.50 SM 04/17/2007 10:39:20 PAGE 6
302 //----------------------------------------------------------------------------
303 // Description:
304 // Read one page of data from SmartMedia to FIFO
305 //----------------------------------------------------------------------------
306 STATUS SmReadPage (UINT32 Page)
307 {
308 1 STATUS RetVal;
309 1 BYTE RetryCount;
310 1
311 1 for (RetryCount = 0; RetryCount < 3; RetryCount++)
312 1 {
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