91x_init.s

基于STR912的GPIO程序,本示例程序主要为测试GPIO功能。当程序运行时

;******************** (C) COPYRIGHT 2006 STMicroelectronics ********************
;* File Name          : 91x_init.s
;* Author             : MCD Application Team
;* Date First Issued  :  05/18/2006 : Version 1.0
;* Description        : This module performs:
;*                      - FLASH/RAM initialization,
;*                      - Stack pointer initialization for each mode ,
;*                      - Branches to __main in the C library (which eventually 
;*                        calls main()).
;*
;*		      On reset, the ARM core starts up in Supervisor (SVC) mode,
;*		      in ARM state,with IRQ and FIQ disabled.
;*******************************************************************************
; History:
; 05/24/2006 : Version 1.1
; 05/18/2006 : Version 1.0
;*******************************************************************************
;* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH
;* CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS
;* A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT
;* OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT
;* OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION
;* CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
;******************************************************************************/

        
        PRESERVE8
        AREA    Init, CODE, READONLY
        
        IMPORT  |Image$$RW_IRAM1$$Limit|

        EXPORT	__user_initial_stackheap
        
; Ensure no functions that use semihosting SWIs are linked in from the C library
; Comment this line if application uses SWI

       ;IMPORT __use_no_semihosting_swi

; Depending in Your Application, Disable or Enable the following Define

  GBLL BUFFERED_Mode       ; Work on Buffered mode, when enabling this define
                           ; just enable the Buffered define on 91x_conf.h

; --- Standard definitions of mode bits and interrupt (I & F) flags in PSRs

Mode_USR           EQU     0x10
Mode_FIQ           EQU     0x11
Mode_IRQ           EQU     0x12
Mode_SVC           EQU     0x13
Mode_ABT           EQU     0x17
Mode_UND           EQU     0x1B
Mode_SYS           EQU     0x1F ; available on ARM Arch 4 and later

I_Bit              EQU     0x80 ; when I bit is set, IRQ is disabled
F_Bit              EQU     0x40 ; when F bit is set, FIQ is disabled

;--- BASE ADDRESSES
; System memory locations

RAM_Base       EQU     0x04000000
RAM_Limit      EQU     0x04018000          ; at the top of 96 KB SRAM

; STR9X register specific definition

SCRO_AHB_UNB    EQU     0x5C002034

; --- Amount of memory (in bytes) allocated for stacks

Stack_Base          EQU    RAM_Limit

USR_Stack_Length    EQU    1024
IRQ_Stack_Length    EQU    256
SVC_Stack_Length    EQU    64
FIQ_Stack_Length    EQU    64
ABT_Stack_Length    EQU    0
UND_Stack_Length    EQU    0

; Add lengths >0 for  ABT_Stack, UND_Stack if you need them.
; Offsets will be loaded as immediate values.
; Offsets must be 8 byte aligned.

Offset_FIQ_Stack         EQU     0
Offset_IRQ_Stack         EQU     Offset_FIQ_Stack + FIQ_Stack_Length
Offset_ABT_Stack         EQU     Offset_IRQ_Stack + IRQ_Stack_Length
Offset_UND_Stack         EQU     Offset_ABT_Stack + ABT_Stack_Length
Offset_SVC_Stack         EQU     Offset_UND_Stack + UND_Stack_Length
Offset_USR_Stack         EQU     Offset_SVC_Stack + SVC_Stack_Length




        EXPORT  Reset_Handler

Reset_Handler
        LDR     pc, = NextInst

NextInst


        NOP  ; execute some instructions to access CPU registers after wake
        NOP  ; up from Reset, while waiting for OSC stabilization
        NOP
        NOP
        NOP
        NOP
        NOP
        NOP
        NOP

  IF :DEF: BUFFERED_Mode

  ; BUFFERED_Mode
  ; -------------------------------------------------------------------------------
  ; Description  :   Enable the Buffered mode.
  ;                  When enable, just enable the buffered define on the 91x_conf.h
  ; http://www.arm.com/pdfs/DDI0164A_966E_S.pdf 
  ; -------------------------------------------------------------------------------

        MRC     p15, 0, r0, c1, c0, 0   ; Read CP15 register 1 into r0
	  ORR     r0, r0, #0x8            ; Enable Write Buffer on AHB
        MCR     p15, 0, r0, c1, c0, 0   ; Write CP15 register 1
  ENDIF


; --- Remap Flash Bank 0 at address 0x0 and Bank 1 at address 0x80000, 
;     when the bank 0 is the boot bank, then enable the Bank 1.

        LDR R6, =0x54000000
        LDR R7, =0x4
        STR R7, [R6]

        LDR R6, =0x54000004
        LDR R7, =0x3
        STR R7, [R6]

        LDR R6, =0x5400000C
        LDR R7, =0x0
        STR R7, [R6]

        LDR R6, =0x54000010
        LDR R7, =0x20000
        STR R7, [R6]

        LDR R6, =0x54000018
        LDR R7, =0x18
        STR R7, [R6]

; --- Enable 96K RAM
        LDR     R0, = SCRO_AHB_UNB
        LDR     R1, = 0x0196
        STR     R1, [R0]
        
; --- Initialize stack pointer registers

        ; Enter each mode in turn and set up the stack pointer
        LDR     r0, =Stack_Base  ; top of stack region

        MSR     CPSR_c, #Mode_FIQ:OR:I_Bit:OR:F_Bit ; No interrupts
        MOV     sp, r0
		SUB     R0, r0, #Offset_FIQ_Stack

        MSR     CPSR_c, #Mode_IRQ:OR:I_Bit:OR:F_Bit ; No interrupts
        MOV     SP, R0
		SUB     r0, r0, #Offset_IRQ_Stack

        MSR     CPSR_c, #Mode_ABT:OR:I_Bit:OR:F_Bit ; No interrupts
        MOV     sp, r0 
		SUB     r0, r0, #Offset_ABT_Stack

        MSR     CPSR_c, #Mode_UND:OR:I_Bit:OR:F_Bit ; No interrupts
        MOV     sp, r0
		SUB     r0, r0, #Offset_UND_Stack

        MSR     CPSR_c, #Mode_SVC:OR:I_Bit:OR:F_Bit ; No interrupts
        MOV     sp, r0
		SUB     r0, r0, #Offset_SVC_Stack
 

; --- Set bits 17-18 of the core Configuration Control Register

      MOV     r0, #0x60000
      MCR     p15,0x1,r0,c15,c1,0

; --- Now change to USR/SYS mode and set up User mode stack,

        LDR     r0, =Stack_Base  ; Top of stack region
        MSR     CPSR_c, #Mode_SYS               ; IRQs & FIQs are now enabled
		MOV     sp, r0
        SUB     r0, r0, #Offset_USR_Stack


      IMPORT  __main

; --- Now enter the C code
      B       __main   ; Note : use B not BL, because an application will
                       ; never return this way
                       
                       
; Implementation of __user_initial_stackheap that places the heap at
; the location of the symbol Image$$HEAP$$ZI$$Base placed by the scatter file.
  

__user_initial_stackheap    

    LDR   r0, =|Image$$RW_IRAM1$$Limit|
    BX    lr


      LTORG


      END
;******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****