pll.asm

基于ti tms320c6713下MSBSP、EDMA 配置和简单FIR算法的一个例子

;******************************************************************************
;* TMS320C6x C/C++ Codegen                                    PC Version 4.32 *
;* Date/Time created: Thu May 29 11:48:33 2008                                *
;******************************************************************************

;******************************************************************************
;* GLOBAL FILE PARAMETERS                                                     *
;*                                                                            *
;*   Architecture      : TMS320C670x                                          *
;*   Optimization      : Enabled at level 3                                   *
;*   Optimizing for    : Speed                                                *
;*                       Based on options: -o3, no -ms                        *
;*   Endian            : Little                                               *
;*   Interrupt Thrshld : Disabled                                             *
;*   Memory Model      : Small                                                *
;*   Calls to RTS      : Near                                                 *
;*   Pipelining        : Enabled                                              *
;*   Speculative Load  : Disabled                                             *
;*   Memory Aliases    : Presume are aliases (pessimistic)                    *
;*   Debug Info        : No Debug Info                                        *
;*                                                                            *
;******************************************************************************

	.asg	A15, FP
	.asg	B14, DP
	.asg	B15, SP
	.global	$bss

;	e:\ti\c6000\cgtools\bin\opt6x.exe -v6700 -q -s -O3 D:\DOCUME~1\davis\LOCALS~1\Temp\TI2960_2 D:\DOCUME~1\davis\LOCALS~1\Temp\TI2960_5 -w C:/c6713/Source Code/DSPSRC/Audiocfg_FIR/Release 

	.sect	".text"
	.global	_plldelay

;******************************************************************************
;* FUNCTION NAME: _plldelay                                                   *
;*                                                                            *
;*   Regs Modified     :                                                      *
;*   Regs Used         : B3                                                   *
;*   Local Frame Size  : 0 Args + 0 Auto + 0 Save = 0 byte                    *
;******************************************************************************
_plldelay:
;** --------------------------------------------------------------------------*
;** 20	-----------------------    if ( !delaynum ) goto g2;
;**  	-----------------------    #pragma LOOP_FLAGS(4096u)
;       ----------------------- /* EMPTY LOOP DELETED */ 
;**	-----------------------g2:
;**  	-----------------------    return;
           RET     .S2     B3                ; |21| 
           NOP             5
           ; BRANCH OCCURS                   ; |21| 



	.sect	".text"
	.global	_PLLInit

;******************************************************************************
;* FUNCTION NAME: _PLLInit                                                    *
;*                                                                            *
;*   Regs Modified     : A0,A3,A4,B4,B5,B6                                    *
;*   Regs Used         : A0,A3,A4,B3,B4,B5,B6                                 *
;*   Local Frame Size  : 0 Args + 0 Auto + 0 Save = 0 byte                    *
;******************************************************************************
_PLLInit:
;** --------------------------------------------------------------------------*
;** 24	-----------------------    *(volatile unsigned *)0x1b7c100u &= 0xfffffffeu;
;** 26	-----------------------    *(volatile unsigned *)0x1b7c100u |= 0x8u;
;** 28	-----------------------    *(volatile unsigned *)0x1b7c114u = C$1 = 32768u;
;** 29	-----------------------    *(volatile unsigned *)0x1b7c110u = 17u;
;** 31	-----------------------    *(volatile unsigned *)0x1b7c124u = C$1;
;** 32	-----------------------    *(volatile unsigned *)0x1b7c120u = C$2 = 32769u;
;** 33	-----------------------    *(volatile unsigned *)0x1b7c11cu = C$2;
;** 34	-----------------------    *(volatile unsigned *)0x1b7c118u = C$1;
;** 35	-----------------------    *(volatile unsigned *)0x1b7c100u &= 0xfffffff7u;
;** 37	-----------------------    *(volatile unsigned *)0x1b7c100u |= 1u;
;** 38	-----------------------    return;
           MVKL    .S2     0x1b7c100,B4      ; |24| 
           MVKH    .S2     0x1b7c100,B4      ; |24| 
           LDW     .D2T2   *B4,B5            ; |24| 
           MVKL    .S1     0x1b7c100,A0      ; |26| 
           MVKH    .S1     0x1b7c100,A0      ; |26| 
           MVK     .S2     17,B6             ; |29| 
           NOP             1
           AND     .S2     -2,B5,B5          ; |24| 
           STW     .D2T2   B5,*B4            ; |24| 
           LDW     .D1T1   *A0,A3            ; |26| 
           MVKL    .S2     0x1b7c114,B4      ; |28| 
           MVKH    .S2     0x1b7c114,B4      ; |28| 
           ZERO    .D2     B5                ; |28| 
           SET     .S2     B5,0xf,0xf,B5     ; |28| 

           MVKL    .S1     0x1b7c110,A3      ; |29| 
||         OR      .L1     8,A3,A4           ; |26| 

           STW     .D1T1   A4,*A0            ; |26| 
||         MVKH    .S1     0x1b7c110,A3      ; |29| 

           MVKL    .S2     0x1b7c124,B4      ; |31| 
||         STW     .D2T2   B5,*B4            ; |28| 
||         MVK     .S1     32767,A0          ; |32| 

           MVKL    .S1     0x1b7c120,A3      ; |32| 
||         MVKH    .S2     0x1b7c124,B4      ; |31| 
||         STW     .D1T2   B6,*A3            ; |29| 

           MVKL    .S2     0x1b7c11c,B4      ; |33| 
||         ADD     .D1     0x2,A0,A0         ; |32| 
||         MVKH    .S1     0x1b7c120,A3      ; |32| 
||         STW     .D2T2   B5,*B4            ; |31| 

           MVKL    .S1     0x1b7c118,A3      ; |34| 
||         MVKH    .S2     0x1b7c11c,B4      ; |33| 
||         STW     .D1T1   A0,*A3            ; |32| 

           MVKL    .S2     0x1b7c100,B4      ; |35| 
||         MVKH    .S1     0x1b7c118,A3      ; |34| 
||         STW     .D2T1   A0,*B4            ; |33| 

           MVKH    .S2     0x1b7c100,B4      ; |35| 
||         STW     .D1T2   B5,*A3            ; |34| 

           LDW     .D2T2   *B4,B5            ; |35| 
           MVKL    .S1     0x1b7c100,A0      ; |37| 
           MVKH    .S1     0x1b7c100,A0      ; |37| 
           NOP             2
           AND     .S2     -9,B5,B5          ; |35| 
           STW     .D2T2   B5,*B4            ; |35| 
           LDW     .D1T1   *A0,A3            ; |37| 
           RET     .S2     B3                ; |39| 
           NOP             3
           OR      .S1     1,A3,A3           ; |37| 
           STW     .D1T1   A3,*A0            ; |37| 
           ; BRANCH OCCURS                   ; |39|