csl_uhpi.h

基于ti tms320c672x下音频开发例子程式

/*  ============================================================================
 *   Copyright (c) Texas Instruments Inc 2002, 2003, 2004
 *
 *   Use of this software is controlled by the terms and conditions found
 *   in the license agreement under which this software has been supplied.
 *   ===========================================================================
 */

/** @file  csl_uhpi.h
 *
 *  @path $(CSLPATH)\uhpi\v1\src
 *
 *  @brief UHPI functional layer API header file
 *
 */

/** @mainpage UHPI CSL 3.x
 *
 * @section Introduction
 *
 * @subsection xxx Purpose and Scope
 * The purpose of this document is to identify a set of common CSL APIs for
 * the UHPI module across various devices. The CSL developer is expected to
 * refer to this document while designing APIs for these modules. Some of the
 * listed APIs may not be applicable to a given UHPI module. While other cases
 * this list of APIs may not be sufficient to cover all the features of a
 * particular UHPI Module. The CSL developer should use his discretion designing
 * new APIs or extending the existing ones to cover these.
 *
 * @subsection Terms and Abbreviations
 *   -# CSL:  Chip Support Library
 *   -# API:  Application Programmer Interface
 *
 * @subsection References
 *    -# CSL-001-DES, CSL 3.x Design Specification DocumentVersion 1.02
 *
 */

/* =============================================================================
 *
 *  30-Jan-2005 asr File Created.
 * =============================================================================
 */

#ifndef _CSL_UHPI_H_
#define _CSL_UHPI_H_

#ifdef __cplusplus
extern "C" {
#endif

#include <cslr.h>
#include <soc.h>
#include <csl_error.h>
#include <csl_types.h>
#include <csl.h>
#include <cslr_uhpi.h>

/** 
* Enumeration for hardware status query commands
*/

typedef enum {
		/**<
         * @brief   Query the current value of Peripheral Revision
         * @param   (Uint32 *)
         */
    CSL_UHPI_QUERY_PID_REV      = 0,
		/**<
         * @brief   Query the current value of Peripheral Class
         * @param   (Uint32 *)
         */
    CSL_UHPI_QUERY_PID_CLASS    = 1,
		/**<
         * @brief   Query the current value of Peripheral Type
         * @param   (Uint32 *)
         */
    CSL_UHPI_QUERY_PID_TYPE     = 2,
		/**<
         * @brief   Query the current value of GP Interrupt Enable-0
         * @param   (Uint32 *)
         */    
    CSL_UHPI_QUERY_GPINT_EN0    = 3,
		/**<
         * @brief   Query the current value of GP Interrupt Enable 1
         * @param   (Uint32 *)
         */    
    CSL_UHPI_QUERY_GPINT_EN1    = 4,
		/**<
         * @brief   Query the current value of GP Interrupt Enable 2
         * @param   (Uint32 *)
         */    
    CSL_UHPI_QUERY_GPINT_EN2    = 5,
		/**<
         * @brief   Query the current value of GPIO Direction 1
         * @param   (Uint32 *)
         */    
    CSL_UHPI_QUERY_GPIO_DIR1    = 6,
		/**<
         * @brief   Query the current value of GPIO Direction 2
         * @param   (Uint32 *)
         */    
    CSL_UHPI_QUERY_GPIO_DIR2    = 7,
		/**<
         * @brief   Query the current value of GPIO Direction 3
         * @param   (Uint32 *)
         */    
    CSL_UHPI_QUERY_GPIO_DIR3    = 8,
		/**<
         * @brief   Query the current value of Host Ready
         * @param   (Uint32 *)
         */    
    CSL_UHPI_QUERY_HRDY      	= 9,
		/**<
         * @brief   Query the current value of Host Fetch
         * @param   (Uint32 *)
         */    
    CSL_UHPI_QUERY_FETCH    	= 10,
		/**<
         * @brief   Query the current value of HPI Reset
         * @param   (Uint32 *)
         */    
    CSL_UHPI_QUERY_HPI_RST		= 11,
		/**<
         * @brief   Query the current value of Half-word ordering status
         * @param   (Uint32 *)
         */    
    CSL_UHPI_QUERY_HWOB_STAT	= 12
    
}CSL_UhpiHwStatusQuery;

typedef enum {
   		/**<
   		 * @brief	set the GP Interrupt
   		 * @param	Uint32
   		 */
    CSL_UHPI_CMD_GPINT_SET           = 1, 
   		/**<
   		 * @brief	set the GP Interrupt Invert
   		 * @param	Uint32
   		 */    
    CSL_UHPI_CMD_SET_GPINT_INV       = 2, 
   		/**<
   		 * @brief	set the GPIO Enable
   		 * @param	Uint32
   		 */    
    CSL_UHPI_CMD_SET_GPIO_EN         = 3, 
   		/**<
   		 * @brief	set the GPIO Direction-1
   		 * @param	Uint32
   		 */    
    CSL_UHPI_CMD_SET_GPIO_DIR1       = 4, 
   		/**<
   		 * @brief	set the GPIO Direction-2
   		 * @param	Uint16
   		 */    
    CSL_UHPI_CMD_SET_GPIO_DIR2       = 6, 
   		/**<
   		 * @brief	set the GPIO Direction-3
   		 * @param	Uint32
   		 */     
    CSL_UHPI_CMD_SET_GPIO_DIR3       = 7, 
   		/**<
   		 * @brief	Set the HPIC Host-to-DSP Interrupt.
   		 * @param	(None)
   		 */    
    CSL_UHPI_CMD_SET_DSP_INT         = 8,
   		/**<
   		 * @brief	Reset the HPIC Host-to-DSP Interrupt.
   		 * @param	(None)
   		 */    
    CSL_UHPI_CMD_RESET_DSP_INT       = 9,
   		/**<
   		 * @brief	Set the HPIC DSP-to-Host Interrupt.
   		 * @param	(None)
   		 */    
    CSL_UHPI_CMD_SET_HINT            = 10,
   		/**<
   		 * @brief	Reset the HPIC DSP-to-Host Interrupt.
   		 * @param	(None)
   		 */    
    CSL_UHPI_CMD_RESET_HINT          = 11
}CSL_UhpiHwControlCmd;

/**
     @brief Structure configures Host
     Port Interface Write & Read Address 
**/ 

 typedef struct {
     /** Host Port Interface Write Address **/
     Uint32     hpiaWrtAddr;
     /** Host Port Interface Read Address **/
     Uint32     hpiaReadAddr;
     /** eXtended Host Port Interface Write Address **/
     Uint32     extHpiaWrtAddr;
     /** eXtended Host Port Interface Read Address **/
     Uint32     extHpiaReadAddr;
}CSL_UhpiAddrCfg;
 
typedef enum {
	/* Half-word Ordering Bit*/
    CSL_UHPI_HWOB       = 0x1, 
	/* Host-to-DSP Interrupt */
    CSL_UHPI_DSP_INT    = 0x2, 
	/* DSP-to-Host Interrupt */      
    CSL_UHPI_HINT       = 0x4, 
	/* Host Ready */
    CSL_UHPI_HRDY       = 0x8,   
	/* Host Fetch */
    CSL_UHPI_FETCH      = 0x10,  
	/* UHPI Extended Address */
    CSL_UHPI_XHPIA      = 0x20,  
	/* CPU Core Reset */
    CSL_UHPI_RESET      = 0x40,  
	/* HPI Reset */
    CSL_UHPI_HPI_RST    = 0x80,
	/* Half-word ordering bit status */
    CSL_UHPI_HWOB_STAT  = 0x100,
	/* Dual HPIA mode configuration bit */
    CSL_UHPI_DUAL_HPIA  = 0x200, 
	/* Loop-back mode configuration bit */    
    CSL_UHPI_LB_MODE    = 0x400, 
	/*HPIA register select bit */    
    CSL_UHPI_HPIA_RW_SEL= 0x800
}CSL_UhpiCtrl;            
                 
typedef enum {
	/* This DAT bit corresponds to the /HAS pin */
    CSL_UHPI_GPIO_DAT0    = 0x1,
	/* controls/statis the level of the  /HCS pin */    
    CSL_UHPI_GPIO_DAT1    = 0x2,   
	/* controls/statis the  level of the /HDS1 pin */
    CSL_UHPI_GPIO_DAT2    = 0x4,
	/* controls/status the  level of the /HDS1 pin */    
    CSL_UHPI_GPIO_DAT3    = 0x8,   
	/* Controls/status the  level of the HR/W pin */
    CSL_UHPI_GPIO_DAT4    = 0x10,  
	/* controls/status the  level of the HHWIL pin */    
    CSL_UHPI_GPIO_DAT5    = 0x20,  
	/* controls/status the  level of the HCNTLB pin */
    CSL_UHPI_GPIO_DAT6    = 0x40,  
	/* controls/status the level of the HCNTLA pin */    
    CSL_UHPI_GPIO_DAT7    = 0x80,  
	/* controls/status the level of the /HINT pin */    
    CSL_UHPI_GPIO_DAT8    = 0x100, 
	/* control/status the level of the HRDY pin */    
    CSL_UHPI_GPIO_DAT9    = 0x200, 
	/* control/status the level of the /HRDY pin */    
    CSL_UHPI_GPIO_DAT10   = 0x400, 
	/* control/status the level of the /HBE0 pin */
    CSL_UHPI_GPIO_DAT11   = 0x800, 
	/* control/status the level of the /HBE1 pin */    
    CSL_UHPI_GPIO_DAT12   = 0x1000,
	/* control/status the level of the /HBE2 pin */    
    CSL_UHPI_GPIO_DAT13   = 0x2000,
	/* control/status the level of the /HBE3 pin */    
    CSL_UHPI_GPIO_DAT14   = 0x4000
}CSL_UhpiGpioDat2;

typedef enum {
	/* control the direction of the /HAS pin */
    CSL_UHPI_GPIO_DIR0  = 0x1,    
	/* control the direction of the /HCS pin */
    CSL_UHPI_GPIO_DIR1  = 0x2,    
	/* control the direction of the /HDS1 pin */
    CSL_UHPI_GPIO_DIR2  = 0x4,    
	/* control the direction of the /HDS2 pin */
    CSL_UHPI_GPIO_DIR3  = 0x8,    
	/* control the direction of the HR/W pin */    
    CSL_UHPI_GPIO_DIR4  = 0x10,   
	/* control the direction of the HHWIL pin */    
    CSL_UHPI_GPIO_DIR5  = 0x20,   
	/* control the direction of the HCNTLB pin */    
    CSL_UHPI_GPIO_DIR6  = 0x40,   
	/* control the direction of the HCNTLA pin */    
    CSL_UHPI_GPIO_DIR7  = 0x80,   
	/* control the direction of the /HINT pin */    
    CSL_UHPI_GPIO_DIR8  = 0x100,  
	/* control the direction of the HRDY pin */    
    CSL_UHPI_GPIO_DIR9  = 0x200,  
	/* control the direction of the /HRDY pin */
    CSL_UHPI_GPIO_DIR10 = 0x400,  
	/* control the direction of the /HBE0 pin */    
    CSL_UHPI_GPIO_DIR11 = 0x800,  
	/* control the direction of the /HBE1 pin */
    CSL_UHPI_GPIO_DIR12 = 0x1000, 
	/* control the direction of the /HBE2 pin */    
    CSL_UHPI_GPIO_DIR13 = 0x2000, 
	/* control the direction of the /HBE3 pin */    
    CSL_UHPI_GPIO_DIR14 = 0x4000
}CSL_UhpiGpioDir2;

typedef struct {
    /** GPIO Direction - 1 Register **/
    Uint32              gpioData1;
    /** GPIO Direction - 2 Register **/
    CSL_UhpiGpioDat2    gpioData2;
    /** GPIO Direction - 3 Register **/
    Uint32              gpioData3;
}CSL_UhpiGpioData;
 
typedef struct {
    /** GPIO Direction - 1 Register **/
    Uint32              gpioDir1;
    /** GPIO Direction - 2 Register **/
    CSL_UhpiGpioDir2    gpioDir2;
    /** GPIO Direction - 3 Register **/
    Uint32              gpioDir3;
}CSL_UhpiGpioDir;

typedef enum {
	/* GPIO_EN0 bank includes the /HCS /HDS1 /HDS2 pins */
    CSL_UHPI_GPIO_EN0  = 0x1,
	/* GPIO_EN1 bank includes HCNTL[B:A] pins */    
    CSL_UHPI_GPIO_EN1  = 0x2,