📄 cslr_chip.h
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#define CSL_CHIP_FADCR_NAN1_L1_MASK (0x1u)
#define CSL_CHIP_FADCR_NAN1_L1_SHIFT (0x0u)
#define CSL_CHIP_FADCR_NAN1_L1_RESETVAL (0x0u)
/**----NAN1_L1 Tokens----*/
#define CSL_CHIP_FADCR_NAN1_L1_SRC1NONAN (0x0u)
#define CSL_CHIP_FADCR_NAN1_L1_SRC1NAN (0x1u)
#define CSL_CHIP_FADCR_RESETVAL (0x0u)
/*******************************************************************************\
* _____________________
* | |
* | F A U C R |
* |___________________|
*
* FAUCR - floating-point auxiliary config register (1)
*
* FIELDS (msb -> lsb)
* (rw) S2DIV0
* (rw) S2UNORD
* (rw) S2UND
* (rw) S2INEX
* (rw) S2OVER
* (rw) S2INFO
* (rw) S2INVAL
* (rw) S2DEN2
* (rw) S2DEN1
* (rw) S2NAN2
* (rw) S2NAN1
* (rw) S1DIV0
* (rw) S1UNORD
* (rw) S1UND
* (rw) S1INEX
* (rw) S1OVER
* (rw) S1INFO
* (rw) S1INVAL
* (rw) S1DEN2
* (rw) S1DEN1
* (rw) S1NAN2
* (rw) S1NAN1
*
\******************************************************************************/
#define CSL_CHIP_FAUCR_DIVO_S2_MASK (0x4000000u)
#define CSL_CHIP_FAUCR_DIVO_S2_SHIFT (0x1Au)
#define CSL_CHIP_FAUCR_DIVO_S2_RESETVAL (0x0u)
/**----DIVO_S2 Tokens----*/
#define CSL_CHIP_FAUCR_DIVO_S2_ZER0 (0x0u)
#define CSL_CHIP_FAUCR_DIVO_S2_NONZERO (0x1u)
#define CSL_CHIP_FAUCR_UNORD_S2_MASK (0x2000000u)
#define CSL_CHIP_FAUCR_UNORD_S2_SHIFT (0x19u)
#define CSL_CHIP_FAUCR_UNORD_S2_RESETVAL (0x0u)
/**----UNORD_S2 Tokens----*/
#define CSL_CHIP_FAUCR_UNORD_S2_NANNOSRC (0x0u)
#define CSL_CHIP_FAUCR_UNORD_S2_NANSRC (0x1u)
#define CSL_CHIP_FAUCR_UNDER_S2_MASK (0x1000000u)
#define CSL_CHIP_FAUCR_UNDER_S2_SHIFT (0x18u)
#define CSL_CHIP_FAUCR_UNDER_S2_RESETVAL (0x0u)
/**----UNDER_S2 Tokens----*/
#define CSL_CHIP_FAUCR_UNDER_S2_NOOVRFLW (0x0u)
#define CSL_CHIP_FAUCR_UNDER_S2_OVRFLW (0x1u)
#define CSL_CHIP_FAUCR_INEX_S2_MASK (0x800000u)
#define CSL_CHIP_FAUCR_INEX_S2_SHIFT (0x17u)
#define CSL_CHIP_FAUCR_INEX_S2_RESETVAL (0x0u)
/**----INEX_S2 Tokens----*/
#define CSL_CHIP_FAUCR_INEX_S2_CLR (0x0u)
#define CSL_CHIP_FAUCR_INEX_S2_SET (0x1u)
#define CSL_CHIP_FAUCR_OVER_S2_MASK (0x400000u)
#define CSL_CHIP_FAUCR_OVER_S2_SHIFT (0x16u)
#define CSL_CHIP_FAUCR_OVER_S2_RESETVAL (0x0u)
/**----OVER_S2 Tokens----*/
#define CSL_CHIP_FAUCR_OVER_S2_NOOVRFLW (0x0u)
#define CSL_CHIP_FAUCR_OVER_S2_OVRFLW (0x1u)
#define CSL_CHIP_FAUCR_INFO_S2_MASK (0x200000u)
#define CSL_CHIP_FAUCR_INFO_S2_SHIFT (0x15u)
#define CSL_CHIP_FAUCR_INFO_S2_RESETVAL (0x0u)
/**----INFO_S2 Tokens----*/
#define CSL_CHIP_FAUCR_INFO_S2_NOSIGNINF (0x0u)
#define CSL_CHIP_FAUCR_INFO_S2_SIGNINF (0x1u)
#define CSL_CHIP_FAUCR_INVAL_S2_MASK (0x100000u)
#define CSL_CHIP_FAUCR_INVAL_S2_SHIFT (0x14u)
#define CSL_CHIP_FAUCR_INVAL_S2_RESETVAL (0x0u)
/**----INVAL_S2 Tokens----*/
#define CSL_CHIP_FAUCR_INVAL_S2_NANNOSRC (0x0u)
#define CSL_CHIP_FAUCR_INVAL_S2_NANSRC (0x1u)
#define CSL_CHIP_FAUCR_DEN2_S2_MASK (0x80000u)
#define CSL_CHIP_FAUCR_DEN2_S2_SHIFT (0x13u)
#define CSL_CHIP_FAUCR_DEN2_S2_RESETVAL (0x0u)
/**----DEN2_S2 Tokens----*/
#define CSL_CHIP_FAUCR_DEN2_S2_SRC2NODEN (0x0u)
#define CSL_CHIP_FAUCR_DEN2_S2_SRC2DEN (0x1u)
#define CSL_CHIP_FAUCR_DEN1_S2_MASK (0x40000u)
#define CSL_CHIP_FAUCR_DEN1_S2_SHIFT (0x12u)
#define CSL_CHIP_FAUCR_DEN1_S2_RESETVAL (0x0u)
/**----DEN1_S2 Tokens----*/
#define CSL_CHIP_FAUCR_DEN1_S2_SRC1NODEN (0x0u)
#define CSL_CHIP_FAUCR_DEN1_S2_SRC1DEN (0x1u)
#define CSL_CHIP_FAUCR_NAN2_S2_MASK (0x20000u)
#define CSL_CHIP_FAUCR_NAN2_S2_SHIFT (0x11u)
#define CSL_CHIP_FAUCR_NAN2_S2_RESETVAL (0x0u)
/**----NAN2_S2 Tokens----*/
#define CSL_CHIP_FAUCR_NAN2_S2_SRC2NONAN (0x0u)
#define CSL_CHIP_FAUCR_NAN2_S2_SRC2NAN (0x1u)
#define CSL_CHIP_FAUCR_NAN1_S2_MASK (0x10000u)
#define CSL_CHIP_FAUCR_NAN1_S2_SHIFT (0x10u)
#define CSL_CHIP_FAUCR_NAN1_S2_RESETVAL (0x0u)
/**----NAN1_S2 Tokens----*/
#define CSL_CHIP_FAUCR_NAN1_S2_SRC1NONAN (0x0u)
#define CSL_CHIP_FAUCR_NAN1_S2_SRC1NAN (0x1u)
#define CSL_CHIP_FAUCR_DIVO_S1_MASK (0x400u)
#define CSL_CHIP_FAUCR_DIVO_S1_SHIFT (0xAu)
#define CSL_CHIP_FAUCR_DIVO_S1_RESETVAL (0x0u)
/**----DIVO_S1 Tokens----*/
#define CSL_CHIP_FAUCR_DIVO_S1_ZER0 (0x0u)
#define CSL_CHIP_FAUCR_DIVO_S1_NONZERO (0x1u)
#define CSL_CHIP_FAUCR_UNORD_S1_MASK (0x200u)
#define CSL_CHIP_FAUCR_UNORD_S1_SHIFT (0x9u)
#define CSL_CHIP_FAUCR_UNORD_S1_RESETVAL (0x0u)
/**----UNORD_S1 Tokens----*/
#define CSL_CHIP_FAUCR_UNORD_S1_NANNOSRC (0x0u)
#define CSL_CHIP_FAUCR_UNORD_S1_NANSRC (0x1u)
#define CSL_CHIP_FAUCR_UNDER_S1_MASK (0x100u)
#define CSL_CHIP_FAUCR_UNDER_S1_SHIFT (0x8u)
#define CSL_CHIP_FAUCR_UNDER_S1_RESETVAL (0x0u)
/**----UNDER_S1 Tokens----*/
#define CSL_CHIP_FAUCR_UNDER_S1_NOOVRFLW (0x0u)
#define CSL_CHIP_FAUCR_UNDER_S1_OVRFLW (0x1u)
#define CSL_CHIP_FAUCR_INEX_S1_MASK (0x80u)
#define CSL_CHIP_FAUCR_INEX_S1_SHIFT (0x7u)
#define CSL_CHIP_FAUCR_INEX_S1_RESETVAL (0x0u)
/**----INEX_S1 Tokens----*/
#define CSL_CHIP_FAUCR_INEX_S1_CLR (0x0u)
#define CSL_CHIP_FAUCR_INEX_S1_SET (0x1u)
#define CSL_CHIP_FAUCR_OVER_S1_MASK (0x40u)
#define CSL_CHIP_FAUCR_OVER_S1_SHIFT (0x6u)
#define CSL_CHIP_FAUCR_OVER_S1_RESETVAL (0x0u)
/**----OVER_S1 Tokens----*/
#define CSL_CHIP_FAUCR_OVER_S1_NOOVRFLW (0x0u)
#define CSL_CHIP_FAUCR_OVER_S1_OVRFLW (0x1u)
#define CSL_CHIP_FAUCR_INFO_S1_MASK (0x20u)
#define CSL_CHIP_FAUCR_INFO_S1_SHIFT (0x5u)
#define CSL_CHIP_FAUCR_INFO_S1_RESETVAL (0x0u)
/**----INFO_S1 Tokens----*/
#define CSL_CHIP_FAUCR_INFO_S1_NOSIGNINF (0x0u)
#define CSL_CHIP_FAUCR_INFO_S1_SIGNINF (0x1u)
#define CSL_CHIP_FAUCR_INVAL_S1_MASK (0x10u)
#define CSL_CHIP_FAUCR_INVAL_S1_SHIFT (0x4u)
#define CSL_CHIP_FAUCR_INVAL_S1_RESETVAL (0x0u)
/**----INVAL_S1 Tokens----*/
#define CSL_CHIP_FAUCR_INVAL_S1_NANNOSRC (0x0u)
#define CSL_CHIP_FAUCR_INVAL_S1_NANSRC (0x1u)
#define CSL_CHIP_FAUCR_DEN2_S1_MASK (0x8u)
#define CSL_CHIP_FAUCR_DEN2_S1_SHIFT (0x3u)
#define CSL_CHIP_FAUCR_DEN2_S1_RESETVAL (0x0u)
/**----DEN2_S1 Tokens----*/
#define CSL_CHIP_FAUCR_DEN2_S1_SRC2NODEN (0x0u)
#define CSL_CHIP_FAUCR_DEN2_S1_SRC2DEN (0x1u)
#define CSL_CHIP_FAUCR_DEN1_S1_MASK (0x4u)
#define CSL_CHIP_FAUCR_DEN1_S1_SHIFT (0x2u)
#define CSL_CHIP_FAUCR_DEN1_S1_RESETVAL (0x0u)
/**----DEN1_S1 Tokens----*/
#define CSL_CHIP_FAUCR_DEN1_S1_SRC1NODEN (0x0u)
#define CSL_CHIP_FAUCR_DEN1_S1_SRC1DEN (0x1u)
#define CSL_CHIP_FAUCR_NAN2_S1_MASK (0x2u)
#define CSL_CHIP_FAUCR_NAN2_S1_SHIFT (0x1u)
#define CSL_CHIP_FAUCR_NAN2_S1_RESETVAL (0x0u)
/**----NAN2_S1 Tokens----*/
#define CSL_CHIP_FAUCR_NAN2_S1_SRC2NONAN (0x0u)
#define CSL_CHIP_FAUCR_NAN2_S1_SRC2NAN (0x1u)
#define CSL_CHIP_FAUCR_NAN1_S1_MASK (0x1u)
#define CSL_CHIP_FAUCR_NAN1_S1_SHIFT (0x0u)
#define CSL_CHIP_FAUCR_NAN1_S1_RESETVAL (0x0u)
/**----NAN1_S1 Tokens----*/
#define CSL_CHIP_FAUCR_NAN1_S1_SRC1NONAN (0x0u)
#define CSL_CHIP_FAUCR_NAN1_S1_SRC1NAN (0x1u)
#define CSL_CHIP_FAUCR_RESETVAL (0x0u)
/*******************************************************************************\
* _____________________
* | |
* | F M C R |
* |___________________|
*
* FMCR - floating-point multiplier config register (1)
*
* FIELDS (msb -> lsb)
* (rw) M2RMODE
* (rw) M2UNDER
* (rw) M2INEX
* (rw) M2OVER
* (rw) M2INFO
* (rw) M2INVAL
* (rw) M2DEN2
* (rw) M2DEN1
* (rw) M2NAN2
* (rw) M2NAN1
* (rw) M1RMODE
* (rw) M1UNDER
* (rw) M1INEX
* (rw) M1OVER
* (rw) M1INFO
* (rw) M1INVAL
* (rw) M1DEN2
* (rw) M1DEN1
* (rw) M1NAN2
* (rw) M1NAN1
*
\******************************************************************************/
#define CSL_CHIP_FMCR_RMODE_M2_MASK (0x6000000u)
#define CSL_CHIP_FMCR_RMODE_M2_SHIFT (0x19u)
#define CSL_CHIP_FMCR_RMODE_M2_RESETVAL (0x0u)
/**----RMODE_M2 Tokens----*/
#define CSL_CHIP_FMCR_RMODE_M2_RTOFP (0x0u)
#define CSL_CHIP_FMCR_RMODE_M2_RTOZERO (0x1u)
#define CSL_CHIP_FMCR_RMODE_M2_RTOINF (0x10u)
#define CSL_CHIP_FMCR_RMODE_M2_RTONEGINF (0x11u)
#define CSL_CHIP_FMCR_UNDER_M2_MASK (0x1000000u)
#define CSL_CHIP_FMCR_UNDER_M2_SHIFT (0x18u)
#define CSL_CHIP_FMCR_UNDER_M2_RESETVAL (0x0u)
/**----UNDER_M2 Tokens----*/
#define CSL_CHIP_FMCR_UNDER_M2_NOOVRFLW (0x0u)
#define CSL_CHIP_FMCR_UNDER_M2_OVRFLW (0x1u)
#define CSL_CHIP_FMCR_INEX_M2_MASK (0x800000u)
#define CSL_CHIP_FMCR_INEX_M2_SHIFT (0x17u)
#define CSL_CHIP_FMCR_INEX_M2_RESETVAL (0x0u)
/**----INEX_M2 Tokens----*/
#define CSL_CHIP_FMCR_INEX_M2_CLR (0x0u)
#define CSL_CHIP_FMCR_INEX_M2_SET (0x1u)
#define CSL_CHIP_FMCR_OVER_M2_MASK (0x400000u)
#define CSL_CHIP_FMCR_OVER_M2_SHIFT (0x16u)
#define CSL_CHIP_FMCR_OVER_M2_RESETVAL (0x0u)
/**----OVER_M2 Tokens----*/
#define CSL_CHIP_FMCR_OVER_M2_NOOVRFLW (0x0u)
#define CSL_CHIP_FMCR_OVER_M2_OVRFLW (0x1u)
#define CSL_CHIP_FMCR_INFO_M2_MASK (0x200000u)
#define CSL_CHIP_FMCR_INFO_M2_SHIFT (0x15u)
#define CSL_CHIP_FMCR_INFO_M2_RESETVAL (0x0u)
/**----INFO_M2 Tokens----*/
#define CSL_CHIP_FMCR_INFO_M2_NOSIGNINF (0x0u)
#define CSL_CHIP_FMCR_INFO_M2_SIGNINF (0x1u)
#define CSL_CHIP_FMCR_INVAL_M2_MASK (0x100000u)
#define CSL_CHIP_FMCR_INVAL_M2_SHIFT (0x14u)
#define CSL_CHIP_FMCR_INVAL_M2_RESETVAL (0x0u)
/**----INVAL_M2 Tokens----*/
#define CSL_CHIP_FMCR_INVAL_M2_NANNOSRC (0x0u)
#define CSL_CHIP_FMCR_INVAL_M2_NANSRC (0x1u)
#define CSL_CHIP_FMCR_DEN2_M2_MASK (0x80000u)
#define CSL_CHIP_FMCR_DEN2_M2_SHIFT (0x13u)
#define CSL_CHIP_FMCR_DEN2_M2_RESETVAL (0x0u)
/**----DEN2_M2 Tokens----*/
#define CSL_CHIP_FMCR_DEN2_M2_SRC2NODEN (0x0u)
#define CSL_CHIP_FMCR_DEN2_M2_SRC2DEN (0x1u)
#define CSL_CHIP_FMCR_DEN1_M2_MASK (0x40000u)
#define CSL_CHIP_FMCR_DEN1_M2_SHIFT (0x12u)
#define CSL_CHIP_FMCR_DEN1_M2_RESETVAL (0x0u)
/**----DEN1_M2 Tokens----*/
#define CSL_CHIP_FMCR_DEN1_M2_SRC1NODEN (0x0u)
#define CSL_CHIP_FMCR_DEN1_M2_SRC1DEN (0x1u)
#define CSL_CHIP_FMCR_NAN2_M2_MASK (0x20000u)
#define CSL_CHIP_FMCR_NAN2_M2_SHIFT (0x11u)
#define CSL_CHIP_FMCR_NAN2_M2_RESETVAL (0x0u)
/**----NAN2_M2 Tokens----*/
#define CSL_CHIP_FMCR_NAN2_M2_SRC2NONAN (0x0u)
#define CSL_CHIP_FMCR_NAN2_M2_SRC2NAN (0x1u)
#define CSL_CHIP_FMCR_NAN1_M2_MASK (0x10000u)
#define CSL_CHIP_FMCR_NAN1_M2_SHIFT (0x10u)
#define CSL_CHIP_FMCR_NAN1_M2_RESETVAL (0x0u)
/**----NAN1_M2 Tokens----*/
#define CSL_CHIP_FMCR_NAN1_M2_SRC1NONAN (0x0u)
#define CSL_CHIP_FMCR_NAN1_M2_SRC1NAN (0x1u)
#define CSL_CHIP_FMCR_RMODE_M1_MASK (0x600u)
#define CSL_CHIP_FMCR_RMODE_M1_SHIFT (0x9u)
#define CSL_CHIP_FMCR_RMODE_M1_RESETVAL (0x0u)
/**----RMODE_M1 Tokens----*/
#define CSL_CHIP_FMCR_RMODE_M1_RTOFP (0x0u)
#define CSL_CHIP_FMCR_RMODE_M1_RTOZERO (0x1u)
#define CSL_CHIP_FMCR_RMODE_M1_RTOINF (0x10u)
#define CSL_CHIP_FMCR_RMODE_M1_RTONEGINF (0x11u)
#define CSL_CHIP_FMCR_UNDER_M1_MASK (0x100u)
#define CSL_CHIP_FMCR_UNDER_M1_SHIFT (0x8u)
#define CSL_CHIP_FMCR_UNDER_M1_RESETVAL (0x0u)
/**----UNDER_M1 Tokens----*/
#define CSL_CHIP_FMCR_UNDER_M1_NOOVRFLW (0x0u)
#define CSL_CHIP_FMCR_UNDER_M1_OVRFLW (0x1u)
#define CSL_CHIP_FMCR_INEX_M1_MASK (0x80u)
#define CSL_CHIP_FMCR_INEX_M1_SHIFT (0x7u)
#define CSL_CHIP_FMCR_INEX_M1_RESETVAL (0x0u)
/**----INEX_M1 Tokens----*/
#define CSL_CHIP_FMCR_INEX_M1_CLR (0x0u)
#define CSL_CHIP_FMCR_INEX_M1_SET (0x1u)
#define CSL_CHIP_FMCR_OVER_M1_MASK (0x40u)
#define CSL_CHIP_FMCR_OVER_M1_SHIFT (0x6u)
#define CSL_CHIP_FMCR_OVER_M1_RESETVAL (0x0u)
/**----OVER_M1 Tokens----*/
#define CSL_CHIP_FMCR_OVER_M1_NOOVRFLW (0x0u)
#define CSL_CHIP_FMCR_OVER_M1_OVRFLW (0x1u)
#define CSL_CHIP_FMCR_INFO_M1_MASK (0x20u)
#define CSL_CHIP_FMCR_INFO_M1_SHIFT (0x5u)
#define CSL_CHIP_FMCR_INFO_M1_RESETVAL (0x0u)
/**----INFO_M1 Tokens----*/
#define CSL_CHIP_FMCR_INFO_M1_NOSIGNINF (0x0u)
#define CSL_CHIP_FMCR_INFO_M1_SIGNINF (0x1u)
#define CSL_CHIP_FMCR_INVAL_M1_MASK (0x10u)
#define CSL_CHIP_FMCR_INVAL_M1_SHIFT (0x4u)
#define CSL_CHIP_FMCR_INVAL_M1_RESETVAL (0x0u)
/**----INVAL_M1 Tokens----*/
#define CSL_CHIP_FMCR_INVAL_M1_NANNOSRC (0x0u)
#define CSL_CHIP_FMCR_INVAL_M1_NANSRC (0x1u)
#define CSL_CHIP_FMCR_DEN2_M1_MASK (0x8u)
#define CSL_CHIP_FMCR_DEN2_M1_SHIFT (0x3u)
#define CSL_CHIP_FMCR_DEN2_M1_RESETVAL (0x0u)
/**----DEN2_M1 Tokens----*/
#define CSL_CHIP_FMCR_DEN2_M1_SRC2NODEN (0x0u)
#define CSL_CHIP_FMCR_DEN2_M1_SRC2DEN (0x1u)
#define CSL_CHIP_FMCR_DEN1_M1_MASK (0x4u)
#define CSL_CHIP_FMCR_DEN1_M1_SHIFT (0x2u)
#define CSL_CHIP_FMCR_DEN1_M1_RESETVAL (0x0u)
/**----DEN1_M1 Tokens----*/
#define CSL_CHIP_FMCR_DEN1_M1_SRC1NODEN (0x0u)
#define CSL_CHIP_FMCR_DEN1_M1_SRC1DEN (0x1u)
#define CSL_CHIP_FMCR_NAN2_M1_MASK (0x2u)
#define CSL_CHIP_FMCR_NAN2_M1_SHIFT (0x1u)
#define CSL_CHIP_FMCR_NAN2_M1_RESETVAL (0x0u)
/**----NAN2_M1 Tokens----*/
#define CSL_CHIP_FMCR_NAN2_M1_SRC2NONAN (0x0u)
#define CSL_CHIP_FMCR_NAN2_M1_SRC2NAN (0x1u)
#define CSL_CHIP_FMCR_NAN1_M1_MASK (0x1u)
#define CSL_CHIP_FMCR_NAN1_M1_SHIFT (0x0u)
#define CSL_CHIP_FMCR_NAN1_M1_RESETVAL (0x0u)
/**----NAN1_M1 Tokens----*/
#define CSL_CHIP_FMCR_NAN1_M1_SRC1NONAN (0x0u)
#define CSL_CHIP_FMCR_NAN1_M1_SRC1NAN (0x1u)
#define CSL_CHIP_FMCR_RESETVAL (0x0u)
#endif
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