📄 cslr_chip.h
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#define CSL_CHIP_AMR_BK0_RESETVAL (0x0u)
/** BK0 Tokens */
#define CSL_CHIP_AMR_BK0_2 0x00000000u
#define CSL_CHIP_AMR_BK0_4 0x00000001u
#define CSL_CHIP_AMR_BK0_8 0x00000002u
#define CSL_CHIP_AMR_BK0_16 0x00000003u
#define CSL_CHIP_AMR_BK0_32 0x00000004u
#define CSL_CHIP_AMR_BK0_64 0x00000005u
#define CSL_CHIP_AMR_BK0_128 0x00000006u
#define CSL_CHIP_AMR_BK0_256 0x00000007u
#define CSL_CHIP_AMR_BK0_512 0x00000008u
#define CSL_CHIP_AMR_BK0_1K 0x00000009u
#define CSL_CHIP_AMR_BK0_2K 0x0000000Au
#define CSL_CHIP_AMR_BK0_4K 0x0000000Bu
#define CSL_CHIP_AMR_BK0_8K 0x0000000Cu
#define CSL_CHIP_AMR_BK0_16K 0x0000000Du
#define CSL_CHIP_AMR_BK0_32K 0x0000000Eu
#define CSL_CHIP_AMR_BK0_64K 0x0000000Fu
#define CSL_CHIP_AMR_BK0_128K 0x00000010u
#define CSL_CHIP_AMR_BK0_256K 0x00000011u
#define CSL_CHIP_AMR_BK0_512K 0x00000012u
#define CSL_CHIP_AMR_BK0_1M 0x00000013u
#define CSL_CHIP_AMR_BK0_2M 0x00000014u
#define CSL_CHIP_AMR_BK0_4M 0x00000015u
#define CSL_CHIP_AMR_BK0_8M 0x00000016u
#define CSL_CHIP_AMR_BK0_16M 0x00000017u
#define CSL_CHIP_AMR_BK0_32M 0x00000018u
#define CSL_CHIP_AMR_BK0_64M 0x00000019u
#define CSL_CHIP_AMR_BK0_128M 0x0000001Au
#define CSL_CHIP_AMR_BK0_256M 0x0000001Bu
#define CSL_CHIP_AMR_BK0_512M 0x0000001Cu
#define CSL_CHIP_AMR_BK0_1G 0x0000001Du
#define CSL_CHIP_AMR_BK0_2G 0x0000001Eu
#define CSL_CHIP_AMR_BK0_4G 0x0000001Fu
/** BK1 Tokens */
#define CSL_CHIP_AMR_BK1_2 0x00000000u
#define CSL_CHIP_AMR_BK1_4 0x00000001u
#define CSL_CHIP_AMR_BK1_8 0x00000002u
#define CSL_CHIP_AMR_BK1_16 0x00000003u
#define CSL_CHIP_AMR_BK1_32 0x00000004u
#define CSL_CHIP_AMR_BK1_64 0x00000005u
#define CSL_CHIP_AMR_BK1_128 0x00000006u
#define CSL_CHIP_AMR_BK1_256 0x00000007u
#define CSL_CHIP_AMR_BK1_512 0x00000008u
#define CSL_CHIP_AMR_BK1_1K 0x00000009u
#define CSL_CHIP_AMR_BK1_2K 0x0000000Au
#define CSL_CHIP_AMR_BK1_4K 0x0000000Bu
#define CSL_CHIP_AMR_BK1_8K 0x0000000Cu
#define CSL_CHIP_AMR_BK1_16K 0x0000000Du
#define CSL_CHIP_AMR_BK1_32K 0x0000000Eu
#define CSL_CHIP_AMR_BK1_64K 0x0000000Fu
#define CSL_CHIP_AMR_BK1_128K 0x00000010u
#define CSL_CHIP_AMR_BK1_256K 0x00000011u
#define CSL_CHIP_AMR_BK1_512K 0x00000012u
#define CSL_CHIP_AMR_BK1_1M 0x00000013u
#define CSL_CHIP_AMR_BK1_2M 0x00000014u
#define CSL_CHIP_AMR_BK1_4M 0x00000015u
#define CSL_CHIP_AMR_BK1_8M 0x00000016u
#define CSL_CHIP_AMR_BK1_16M 0x00000017u
#define CSL_CHIP_AMR_BK1_32M 0x00000018u
#define CSL_CHIP_AMR_BK1_64M 0x00000019u
#define CSL_CHIP_AMR_BK1_128M 0x0000001Au
#define CSL_CHIP_AMR_BK1_256M 0x0000001Bu
#define CSL_CHIP_AMR_BK1_512M 0x0000001Cu
#define CSL_CHIP_AMR_BK1_1G 0x0000001Du
#define CSL_CHIP_AMR_BK1_2G 0x0000001Eu
#define CSL_CHIP_AMR_BK1_4G 0x0000001Fu
#define CSL_CHIP_AMR_B7MODE_MASK (0xC000u)
#define CSL_CHIP_AMR_B7MODE_SHIFT (0xEu)
#define CSL_CHIP_AMR_B7MODE_RESETVAL (0x0u)
/** B7 Mode Tokens */
#define CSL_CHIP_AMR_B7MODE_LINEAR 0x00000000u
#define CSL_CHIP_AMR_B7MODE_CIRCULAR0 0x00000001u
#define CSL_CHIP_AMR_B7MODE_CIRCULAR1 0x00000002u
#define CSL_CHIP_AMR_B6MODE_MASK (0x3000u)
#define CSL_CHIP_AMR_B6MODE_SHIFT (0xCu)
#define CSL_CHIP_AMR_B6MODE_RESETVAL (0x0u)
/** B6 Mode Tokens */
#define CSL_CHIP_AMR_B6MODE_LINEAR 0x00000000u
#define CSL_CHIP_AMR_B6MODE_CIRCULAR0 0x00000001u
#define CSL_CHIP_AMR_B6MODE_CIRCULAR1 0x00000002u
#define CSL_CHIP_AMR_B5MODE_MASK (0xC00u)
#define CSL_CHIP_AMR_B5MODE_SHIFT (0xAu)
#define CSL_CHIP_AMR_B5MODE_RESETVAL (0x0u)
/** B5 Mode Tokens */
#define CSL_CHIP_AMR_B5MODE_LINEAR 0x00000000u
#define CSL_CHIP_AMR_B5MODE_CIRCULAR0 0x00000001u
#define CSL_CHIP_AMR_B5MODE_CIRCULAR1 0x00000002u
#define CSL_CHIP_AMR_B4MODE_MASK (0x300u)
#define CSL_CHIP_AMR_B4MODE_SHIFT (0x8u)
#define CSL_CHIP_AMR_B4MODE_RESETVAL (0x0u)
/** B4 Mode Tokens */
#define CSL_CHIP_AMR_B4MODE_LINEAR 0x00000000u
#define CSL_CHIP_AMR_B4MODE_CIRCULAR0 0x00000001u
#define CSL_CHIP_AMR_B4MODE_CIRCULAR1 0x00000002u
#define CSL_CHIP_AMR_A7MODE_MASK (0xC0u)
#define CSL_CHIP_AMR_A7MODE_SHIFT (0x6u)
#define CSL_CHIP_AMR_A7MODE_RESETVAL (0x0u)
/** A7 Mode Tokens */
#define CSL_CHIP_AMR_A7MODE_LINEAR 0x00000000u
#define CSL_CHIP_AMR_A7MODE_CIRCULAR0 0x00000001u
#define CSL_CHIP_AMR_A7MODE_CIRCULAR1 0x00000002u
#define CSL_CHIP_AMR_A6MODE_MASK (0x30u)
#define CSL_CHIP_AMR_A6MODE_SHIFT (0x4u)
#define CSL_CHIP_AMR_A6MODE_RESETVAL (0x0u)
/** A6 Mode Tokens */
#define CSL_CHIP_AMR_A6MODE_LINEAR 0x00000000u
#define CSL_CHIP_AMR_A6MODE_CIRCULAR0 0x00000001u
#define CSL_CHIP_AMR_A6MODE_CIRCULAR1 0x00000002u
#define CSL_CHIP_AMR_A5MODE_MASK (0xCu)
#define CSL_CHIP_AMR_A5MODE_SHIFT (0x2u)
#define CSL_CHIP_AMR_A5MODE_RESETVAL (0x0u)
/** A5 Mode Tokens */
#define CSL_CHIP_AMR_A5MODE_LINEAR 0x00000000u
#define CSL_CHIP_AMR_A5MODE_CIRCULAR0 0x00000001u
#define CSL_CHIP_AMR_A5MODE_CIRCULAR1 0x00000002u
#define CSL_CHIP_AMR_A4MODE_MASK (0x3u)
#define CSL_CHIP_AMR_A4MODE_SHIFT (0x0u)
#define CSL_CHIP_AMR_A4MODE_RESETVAL (0x0u)
/** A4 Mode Tokens */
#define CSL_CHIP_AMR_A4MODE_LINEAR 0x00000000u
#define CSL_CHIP_AMR_A4MODE_CIRCULAR0 0x00000001u
#define CSL_CHIP_AMR_A4MODE_CIRCULAR1 0x00000002u
#define CSL_CHIP_AMR_RESETVAL (0x0u)
/*******************************************************************************\
* _____________________
* | |
* | C S R |
* |___________________|
*
* CSR - control/status register
*
* FIELDS (msb -> lsb)
* (r) CPUID
* (r) REVID
* (rw) PWRD
* (rc) SAT
* (r) EN
* (rw) PCC
* (rw) DCC
* (rw) PGIE
* (rw) GIE
*
\******************************************************************************/
#define CSL_CHIP_CSR_CPUID_MASK (0xFF000000u)
#define CSL_CHIP_CSR_CPUID_SHIFT (0x18u)
#define CSL_CHIP_CSR_CPUID_RESETVAL (0x0u)
#define CSL_CHIP_CSR_REVISIONID_MASK (0xFF0000u)
#define CSL_CHIP_CSR_REVISIONID_SHIFT (0x10u)
#define CSL_CHIP_CSR_REVISIONID_RESETVAL (0x0u)
#define CSL_CHIP_CSR_PWRD_MASK (0xFC00u)
#define CSL_CHIP_CSR_PWRD_SHIFT (0xAu)
#define CSL_CHIP_CSR_PWRD_RESETVAL (0x0u)
/**----PWRD Tokens----*/
#define CSL_CHIP_CSR_PWRD_NO_PWRD (0x0u)
#define CSL_CHIP_CSR_PWRD_PD1I (0x1001u)
#define CSL_CHIP_CSR_PWRD_PD1 (0x10001u)
#define CSL_CHIP_CSR_PWRD_PD2 (0x11010u)
#define CSL_CHIP_CSR_PWRD_PD3 (0x11100u)
#define CSL_CHIP_CSR_SAT_MASK (0x200u)
#define CSL_CHIP_CSR_SAT_SHIFT (0x9u)
#define CSL_CHIP_CSR_SAT_RESETVAL (0x0u)
/**----Sat Tokens----*/
#define CSL_CHIP_CSR_SAT_CLR (0x0u)
#define CSL_CHIP_CSR_SAT_SET (0x1u)
#define CSL_CHIP_CSR_EN_MASK (0x100u)
#define CSL_CHIP_CSR_EN_SHIFT (0x8u)
#define CSL_CHIP_CSR_EN_RESETVAL (0x1u)
/**----EN Tokens----*/
#define CSL_CHIP_CSR_EN_BIG (0x0u)
#define CSL_CHIP_CSR_EN_LITTLE (0x1u)
#define CSL_CHIP_CSR_PCC_MASK (0xE0u)
#define CSL_CHIP_CSR_PCC_SHIFT (0x5u)
#define CSL_CHIP_CSR_PCC_RESETVAL (0x0u)
/**----PCC Tokens----*/
#define CSL_CHIP_CSR_PCC_PCACHE_EN (0x0u)
#define CSL_CHIP_CSR_PCC_PCACHE_ACCESSED (0x10u)
#define CSL_CHIP_CSR_DCC_MASK (0x1Cu)
#define CSL_CHIP_CSR_DCC_SHIFT (0x2u)
#define CSL_CHIP_CSR_DCC_RESETVAL (0x0u)
/**----DCC Tokens----*/
#define CSL_CHIP_CSR_DCC_DCACHE_EN (0x0u)
#define CSL_CHIP_CSR_DCC_DCACHE_ACCESSED (0x10u)
#define CSL_CHIP_CSR_PGIE_MASK (0x2u)
#define CSL_CHIP_CSR_PGIE_SHIFT (0x1u)
#define CSL_CHIP_CSR_PGIE_RESETVAL (0x0u)
/**----PGIE Tokens----*/
#define CSL_CHIP_CSR_PGIE_CLR (0x0u)
#define CSL_CHIP_CSR_PGIE_SET (0x1u)
#define CSL_CHIP_CSR_GIE_MASK (0x1u)
#define CSL_CHIP_CSR_GIE_SHIFT (0x0u)
#define CSL_CHIP_CSR_GIE_RESETVAL (0x0u)
/**----GIE Tokens----*/
#define CSL_CHIP_CSR_GIE_ENABLE (0x0u)
#define CSL_CHIP_CSR_GIE_DISABLE (0x1u)
#define CSL_CHIP_CSR_RESETVAL (0x100u)
/*******************************************************************************\
* _____________________
* | |
* | F A D C R |
* |___________________|
*
* FADCR - floating-point adder config register (1)
*
* FIELDS (msb -> lsb)
* (rw) L2RMODE
* (rw) L2UNDER
* (rw) L2INEX
* (rw) L2OVER
* (rw) L2INFO
* (rw) L2INVAL
* (rw) L2DEN2
* (rw) L2DEN1
* (rw) L2NAN2
* (rw) L2NAN1
* (rw) L1RMODE
* (rw) L1UNDER
* (rw) L1INEX
* (rw) L1OVER
* (rw) L1INFO
* (rw) L1INVAL
* (rw) L1DEN2
* (rw) L1DEN1
* (rw) L1NAN2
* (rw) L1NAN1
\******************************************************************************/
#define CSL_CHIP_FADCR_RMODE_L2_MASK (0x6000000u)
#define CSL_CHIP_FADCR_RMODE_L2_SHIFT (0x19u)
#define CSL_CHIP_FADCR_RMODE_L2_RESETVAL (0x0u)
/**----RMODE_L2 Tokens----*/
#define CSL_CHIP_FADCR_RMODE_L2_RTOFP (0x0u)
#define CSL_CHIP_FADCR_RMODE_L2_RTOZERO (0x1u)
#define CSL_CHIP_FADCR_RMODE_L2_RTOINF (0x10u)
#define CSL_CHIP_FADCR_RMODE_L2_RTONEGINF (0x11u)
#define CSL_CHIP_FADCR_UNDER_L2_MASK (0x1000000u)
#define CSL_CHIP_FADCR_UNDER_L2_SHIFT (0x18u)
#define CSL_CHIP_FADCR_UNDER_L2_RESETVAL (0x0u)
/**----UNDER_L2 Tokens----*/
#define CSL_CHIP_FADCR_UNDER_L2_NOOVRFLW (0x0u)
#define CSL_CHIP_FADCR_UNDER_L2_OVRFLW (0x1u)
#define CSL_CHIP_FADCR_INEX_L2_MASK (0x800000u)
#define CSL_CHIP_FADCR_INEX_2_SHIFT (0x17u)
#define CSL_CHIP_FADCR_INEX_L2_RESETVAL (0x0u)
/**----INEX_L2 Tokens----*/
#define CSL_CHIP_FADCR_INEX_L2_SET (0x0u)
#define CSL_CHIP_FADCR_INEX_L2_CLR (0x1u)
#define CSL_CHIP_FADCR_OVER_L2_MASK (0x400000u)
#define CSL_CHIP_FADCR_OVER_L2_SHIFT (0x16u)
#define CSL_CHIP_FADCR_OVER_L2_RESETVAL (0x0u)
/**----OVER_L2 Tokens----*/
#define CSL_CHIP_FADCR_OVER_L2_NOOVRFLW (0x0u)
#define CSL_CHIP_FADCR_OVER_L2_OVRFLW (0x1u)
#define CSL_CHIP_FADCR_INFO_L2_MASK (0x200000u)
#define CSL_CHIP_FADCR_INFO_L2_SHIFT (0x15u)
#define CSL_CHIP_FADCR_INFO_L2_RESETVAL (0x0u)
/**----INFO_L2 Tokens----*/
#define CSL_CHIP_FADCR_INFO_L2_NOSIGNINF (0x0u)
#define CSL_CHIP_FADCR_INFO_L2_SIGNINF (0x1u)
#define CSL_CHIP_FADCR_INVAL_L2_MASK (0x100000u)
#define CSL_CHIP_FADCR_INVAL_L2_SHIFT (0x14u)
#define CSL_CHIP_FADCR_INVAL_L2_RESETVAL (0x0u)
/**----INVAL_L2 Tokens----*/
#define CSL_CHIP_FADCR_INVAL_L2_NANNOSRC (0x0u)
#define CSL_CHIP_FADCR_INVAL_L2_NANSRC (0x1u)
#define CSL_CHIP_FADCR_DEN2_L2_MASK (0x80000u)
#define CSL_CHIP_FADCR_DEN2_L2_SHIFT (0x13u)
#define CSL_CHIP_FADCR_DEN2_L2_RESETVAL (0x0u)
/**----DEN2_L2 Tokens----*/
#define CSL_CHIP_FADCR_DEN2_L2_SRC2NODEN (0x0u)
#define CSL_CHIP_FADCR_DEN2_L2_SRC2DEN (0x1u)
#define CSL_CHIP_FADCR_DEN1_L2_MASK (0x40000u)
#define CSL_CHIP_FADCR_DEN1_L2_SHIFT (0x12u)
#define CSL_CHIP_FADCR_DEN1_L2_RESETVAL (0x0u)
/**----DEN1_L2 Tokens----*/
#define CSL_CHIP_FADCR_DEN1_L2_SRC1NODEN (0x0u)
#define CSL_CHIP_FADCR_DEN1_L2_SRC1DEN (0x1u)
#define CSL_CHIP_FADCR_NAN2_L2_MASK (0x20000u)
#define CSL_CHIP_FADCR_NAN2_L2_SHIFT (0x11u)
#define CSL_CHIP_FADCR_NAN2_L2_RESETVAL (0x0u)
/**----NAN2_L2 Tokens----*/
#define CSL_CHIP_FADCR_NAN2_L2_SRC2NONAN (0x0u)
#define CSL_CHIP_FADCR_NAN2_L2_SRC2NAN (0x1u)
#define CSL_CHIP_FADCR_NAN1_L2_MASK (0x10000u)
#define CSL_CHIP_FADCR_NAN1_L2_SHIFT (0x10u)
#define CSL_CHIP_FADCR_NAN1_L2_RESETVAL (0x0u)
/**----NAN1_L2 Tokens----*/
#define CSL_CHIP_FADCR_NAN1_L2_SRC1NONAN (0x0u)
#define CSL_CHIP_FADCR_NAN1_L2_SRC1NAN (0x1u)
#define CSL_CHIP_FADCR_RMODE_L1_MASK (0x600u)
#define CSL_CHIP_FADCR_RMODE_L1_SHIFT (0x9u)
#define CSL_CHIP_FADCR_RMODE_L1_RESETVAL (0x0u)
/**----RMODE_L1 Tokens----*/
#define CSL_CHIP_FADCR_RMODE_L1_RTOFP (0x0u)
#define CSL_CHIP_FADCR_RMODE_L1_RTOZERO (0x1u)
#define CSL_CHIP_FADCR_RMODE_L1_RTOINF (0x10u)
#define CSL_CHIP_FADCR_RMODE_L1_RTONEGINF (0x11u)
#define CSL_CHIP_FADCR_UNDER_L1_MASK (0x100u)
#define CSL_CHIP_FADCR_UNDER_L1_SHIFT (0x8u)
#define CSL_CHIP_FADCR_UNDER_L1_RESETVAL (0x0u)
/**----UNDER_L1 Tokens----*/
#define CSL_CHIP_FADCR_UNDER_L1_NOOVRFLW (0x0u)
#define CSL_CHIP_FADCR_UNDER_L1_OVRFLW (0x1u)
#define CSL_CHIP_FADCR_INEX_L1_MASK (0x80u)
#define CSL_CHIP_FADCR_INEX_L1_SHIFT (0x7u)
#define CSL_CHIP_FADCR_INEX_L1_RESETVAL (0x0u)
/**----INEX_L1 Tokens----*/
#define CSL_CHIP_FADCR_INEX_L1_CLR (0x0u)
#define CSL_CHIP_FADCR_INEX_L1_SET (0x1u)
#define CSL_CHIP_FADCR_OVER_L1_MASK (0x40u)
#define CSL_CHIP_FADCR_OVER_L1_SHIFT (0x6u)
#define CSL_CHIP_FADCR_OVER_L1_RESETVAL (0x0u)
/**----OVER_L1 Tokens----*/
#define CSL_CHIP_FADCR_OVER_L1_NOOVRFLW (0x0u)
#define CSL_CHIP_FADCR_OVER_L1_OVRFLW (0x1u)
#define CSL_CHIP_FADCR_INFO_L1_MASK (0x20u)
#define CSL_CHIP_FADCR_INFO_L1_SHIFT (0x5u)
#define CSL_CHIP_FADCR_INFO_L1_RESETVAL (0x0u)
/**----INFO_L1 Tokens----*/
#define CSL_CHIP_FADCR_INFO_L1_NOSIGNINF (0x0u)
#define CSL_CHIP_FADCR_INFO_L1_SIGNINF (0x1u)
#define CSL_CHIP_FADCR_INVAL_L1_MASK (0x10u)
#define CSL_CHIP_FADCR_INVAL_L1_SHIFT (0x4u)
#define CSL_CHIP_FADCR_INVAL_L1_RESETVAL (0x0u)
/**----INVAL_L1 Tokens----*/
#define CSL_CHIP_FADCR_INVAL_L1_NANNOSRC (0x0u)
#define CSL_CHIP_FADCR_INVAL_L1_NANSRC (0x1u)
#define CSL_CHIP_FADCR_DEN2_L1_MASK (0x8u)
#define CSL_CHIP_FADCR_DEN2_L1_SHIFT (0x3u)
#define CSL_CHIP_FADCR_DEN2_L1_RESETVAL (0x0u)
/**----DEN2_L1 Tokens----*/
#define CSL_CHIP_FADCR_DEN2_L1_SRC2NODEN (0x0u)
#define CSL_CHIP_FADCR_DEN2_L1_SRC2DEN (0x1u)
#define CSL_CHIP_FADCR_DEN1_L1_MASK (0x4u)
#define CSL_CHIP_FADCR_DEN1_L1_SHIFT (0x2u)
#define CSL_CHIP_FADCR_DEN1_L1_RESETVAL (0x0u)
/**----DEN1_L1 Tokens----*/
#define CSL_CHIP_FADCR_DEN1_L1_SRC1NODEN (0x0u)
#define CSL_CHIP_FADCR_DEN1_L1_SRC1DEN (0x1u)
#define CSL_CHIP_FADCR_NAN2_L1_MASK (0x2u)
#define CSL_CHIP_FADCR_NAN2_L1_SHIFT (0x1u)
#define CSL_CHIP_FADCR_NAN2_L1_RESETVAL (0x0u)
/**----NAN2_L1 Tokens----*/
#define CSL_CHIP_FADCR_NAN2_L1_SRC2NONAN (0x0u)
#define CSL_CHIP_FADCR_NAN2_L1_SRC2NAN (0x1u)
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