📄 cslr_chip.h
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/** ============================================================================
* Copyright (c) Texas Instruments Inc 2002, 2003, 2004
*
* Use of this software is controlled by the terms and conditions found
* in the license agreement under which this software has been supplied.
* ===========================================================================
*/
/** @file cslr_chip.h
*
* @brief CHIP register layer API header file
*
* Revision History
* ================
* 21-Nov-2004 RMathew Created
*/
#ifndef _CSLR_CHIP_H_
#define _CSLR_CHIP_H_
#include <cslr.h>
#include <csl_types.h>
/***************************************************************************\
* Register Overlay Structure
\**************************************************************************/
/**
* Register Overlay structure for memory mapped chip registers
*/
typedef struct {
/** CFGPIN0 */
volatile Uint32 CFGPIN0;
/** CFGPIN1 */
volatile Uint32 CFGPIN1;
/** CGFHPI */
volatile Uint32 CGFHPI;
/** CFGHPIAMSB */
volatile Uint32 CFGHPIAMSB;
/** CFGHPIAUMB */
volatile Uint32 CFGHPIAUMB;
/** CGFRTI */
volatile Uint32 CGFRTI;
/** CGFMCASP0 */
volatile Uint32 CGFMCASP0;
/** CGFMCASP1 */
volatile Uint32 CGFMCASP1;
/** CGFMCASP2 */
volatile Uint32 CGFMCASP2;
/** CGFBRIDGE */
volatile Uint32 CGFBRIDGE;
volatile Uint32 RSVD2[22];
/** IDREG */
volatile Uint32 IDREG;
/** DFT_READ_WRITE */
volatile Uint32 DFT_READ_WRITE;
} CSL_ChipRegs;
/***************************************************************************\
* Field Definition Macros for memory mapped registers
\**************************************************************************/
/** CFGPIN0 - CGFPIN0 Register */
#define CSL_CHIP_CFGPIN0_PINCAP7_MASK (0x00000080u)
#define CSL_CHIP_CFGPIN0_PINCAP7_SHIFT (0x00000007u)
#define CSL_CHIP_CFGPIN0_PINCAP7_RESETVAL (0x00000000u)
/**----PINCAP7 Tokens----*/
#define CSL_CHIP_CFGPIN0_PINCAP7_HIGH (0x00000001u)
#define CSL_CHIP_CFGPIN0_PINCAP7_LOW (0x00000000u)
#define CSL_CHIP_CFGPIN0_PINCAP6_MASK (0x00000040u)
#define CSL_CHIP_CFGPIN0_PINCAP6_SHIFT (0x00000006u)
#define CSL_CHIP_CFGPIN0_PINCAP6_RESETVAL (0x00000000u)
/**----PINCAP6 Tokens----*/
#define CSL_CHIP_CFGPIN0_PINCAP6_HIGH (0x00000001u)
#define CSL_CHIP_CFGPIN0_PINCAP6_LOW (0x00000000u)
#define CSL_CHIP_CFGPIN0_PINCAP5_MASK (0x00000020u)
#define CSL_CHIP_CFGPIN0_PINCAP5_SHIFT (0x00000005u)
#define CSL_CHIP_CFGPIN0_PINCAP5_RESETVAL (0x00000000u)
/**----PINCAP5 Tokens----*/
#define CSL_CHIP_CFGPIN0_PINCAP5_HIGH (0x00000001u)
#define CSL_CHIP_CFGPIN0_PINCAP5_LOW (0x00000000u)
#define CSL_CHIP_CFGPIN0_PINCAP4_MASK (0x00000010u)
#define CSL_CHIP_CFGPIN0_PINCAP4_SHIFT (0x00000004u)
#define CSL_CHIP_CFGPIN0_PINCAP4_RESETVAL (0x00000000u)
/**----PINCAP4 Tokens----*/
#define CSL_CHIP_CFGPIN0_PINCAP4_HIGH (0x00000001u)
#define CSL_CHIP_CFGPIN0_PINCAP4_LOW (0x00000000u)
#define CSL_CHIP_CFGPIN0_PINCAP3_MASK (0x00000008u)
#define CSL_CHIP_CFGPIN0_PINCAP3_SHIFT (0x00000003u)
#define CSL_CHIP_CFGPIN0_PINCAP3_RESETVAL (0x00000000u)
/**----PINCAP3 Tokens----*/
#define CSL_CHIP_CFGPIN0_PINCAP3_HIGH (0x00000001u)
#define CSL_CHIP_CFGPIN0_PINCAP3_LOW (0x00000000u)
#define CSL_CHIP_CFGPIN0_PINCAP2_MASK (0x00000004u)
#define CSL_CHIP_CFGPIN0_PINCAP2_SHIFT (0x00000002u)
#define CSL_CHIP_CFGPIN0_PINCAP2_RESETVAL (0x00000000u)
/**----PINCAP2 Tokens----*/
#define CSL_CHIP_CFGPIN0_PINCAP2_HIGH (0x00000001u)
#define CSL_CHIP_CFGPIN0_PINCAP2_LOW (0x00000000u)
#define CSL_CHIP_CFGPIN0_PINCAP1_MASK (0x00000002u)
#define CSL_CHIP_CFGPIN0_PINCAP1_SHIFT (0x00000001u)
#define CSL_CHIP_CFGPIN0_PINCAP1_RESETVAL (0x00000000u)
/**----PINCAP1 Tokens----*/
#define CSL_CHIP_CFGPIN0_PINCAP1_HIGH (0x00000001u)
#define CSL_CHIP_CFGPIN0_PINCAP1_LOW (0x00000000u)
#define CSL_CHIP_CFGPIN0_PINCAP0_MASK (0x00000001u)
#define CSL_CHIP_CFGPIN0_PINCAP0_SHIFT (0x00000000u)
#define CSL_CHIP_CFGPIN0_PINCAP0_RESETVAL (0x00000000u)
/**----PINCAP0 Tokens----*/
#define CSL_CHIP_CFGPIN0_PINCAP0_HIGH (0x00000001u)
#define CSL_CHIP_CFGPIN0_PINCAP0_LOW (0x00000000u)
#define CSL_CHIP_CFGPIN0_RESETVAL (0x00000000u)
/** CFGPIN1 - CGFPIN1 Register */
#define CSL_CHIP_CFGPIN1_PINCAP15_MASK (0x00000080u)
#define CSL_CHIP_CFGPIN1_PINCAP15_SHIFT (0x00000007u)
#define CSL_CHIP_CFGPIN1_PINCAP15_RESETVAL (0x00000000u)
/**----PINCAP15 Tokens----*/
#define CSL_CHIP_CFGPIN1_PINCAP15_HIGH (0x00000001u)
#define CSL_CHIP_CFGPIN1_PINCAP15_LOW (0x00000000u)
#define CSL_CHIP_CFGPIN1_PINCAP14_MASK (0x00000040u)
#define CSL_CHIP_CFGPIN1_PINCAP14_SHIFT (0x00000006u)
#define CSL_CHIP_CFGPIN1_PINCAP14_RESETVAL (0x00000000u)
/**----PINCAP14 Tokens----*/
#define CSL_CHIP_CFGPIN1_PINCAP14_HIGH (0x00000001u)
#define CSL_CHIP_CFGPIN1_PINCAP14_LOW (0x00000000u)
#define CSL_CHIP_CFGPIN1_PINCAP13_MASK (0x00000020u)
#define CSL_CHIP_CFGPIN1_PINCAP13_SHIFT (0x00000005u)
#define CSL_CHIP_CFGPIN1_PINCAP13_RESETVAL (0x00000000u)
/**----PINCAP13 Tokens----*/
#define CSL_CHIP_CFGPIN1_PINCAP13_HIGH (0x00000001u)
#define CSL_CHIP_CFGPIN1_PINCAP13_LOW (0x00000000u)
#define CSL_CHIP_CFGPIN1_PINCAP12_MASK (0x00000010u)
#define CSL_CHIP_CFGPIN1_PINCAP12_SHIFT (0x00000004u)
#define CSL_CHIP_CFGPIN1_PINCAP12_RESETVAL (0x00000000u)
/**----PINCAP12 Tokens----*/
#define CSL_CHIP_CFGPIN1_PINCAP12_HIGH (0x00000001u)
#define CSL_CHIP_CFGPIN1_PINCAP12_LOW (0x00000000u)
#define CSL_CHIP_CFGPIN1_PINCAP11_MASK (0x00000008u)
#define CSL_CHIP_CFGPIN1_PINCAP11_SHIFT (0x00000003u)
#define CSL_CHIP_CFGPIN1_PINCAP11_RESETVAL (0x00000000u)
/**----PINCAP11 Tokens----*/
#define CSL_CHIP_CFGPIN1_PINCAP11_HIGH (0x00000001u)
#define CSL_CHIP_CFGPIN1_PINCAP11_LOW (0x00000000u)
#define CSL_CHIP_CFGPIN1_PINCAP10_MASK (0x00000004u)
#define CSL_CHIP_CFGPIN1_PINCAP10_SHIFT (0x00000002u)
#define CSL_CHIP_CFGPIN1_PINCAP10_RESETVAL (0x00000000u)
/**----PINCAP10 Tokens----*/
#define CSL_CHIP_CFGPIN1_PINCAP10_HIGH (0x00000001u)
#define CSL_CHIP_CFGPIN1_PINCAP10_LOW (0x00000000u)
#define CSL_CHIP_CFGPIN1_PINCAP9_MASK (0x00000002u)
#define CSL_CHIP_CFGPIN1_PINCAP9_SHIFT (0x00000001u)
#define CSL_CHIP_CFGPIN1_PINCAP9_RESETVAL (0x00000000u)
/**----PINCAP9 Tokens----*/
#define CSL_CHIP_CFGPIN1_PINCAP9_HIGH (0x00000001u)
#define CSL_CHIP_CFGPIN1_PINCAP9_LOW (0x00000000u)
#define CSL_CHIP_CFGPIN1_PINCAP8_MASK (0x00000001u)
#define CSL_CHIP_CFGPIN1_PINCAP8_SHIFT (0x00000000u)
#define CSL_CHIP_CFGPIN1_PINCAP8_RESETVAL (0x00000000u)
/**----PINCAP8 Tokens----*/
#define CSL_CHIP_CFGPIN1_PINCAP8_HIGH (0x00000001u)
#define CSL_CHIP_CFGPIN1_PINCAP8_LOW (0x00000000u)
#define CSL_CHIP_CFGPIN1_RESETVAL (0x00000000u)
/** CGFHPI - CFGHPI Register */
#define CSL_CHIP_CGFHPI_BYTEAD_MASK (0x00000010u)
#define CSL_CHIP_CGFHPI_BYTEAD_SHIFT (0x00000004u)
#define CSL_CHIP_CGFHPI_BYTEAD_RESETVAL (0x00000000u)
/**----BYTEAD Tokens----*/
#define CSL_CHIP_CGFHPI_BYTEAD_WADDR (0x00000000u)
#define CSL_CHIP_CGFHPI_BYTEAD_BADDR (0x00000001u)
#define CSL_CHIP_CGFHPI_FULL_MASK (0x00000008u)
#define CSL_CHIP_CGFHPI_FULL_SHIFT (0x00000003u)
#define CSL_CHIP_CGFHPI_FULL_RESETVAL (0x00000000u)
/**----FULL Tokens----*/
#define CSL_CHIP_CGFHPI_FULL_HALF (0x00000000u)
#define CSL_CHIP_CGFHPI_FULL_FULL (0x00000001u)
#define CSL_CHIP_CGFHPI_NMUX_MASK (0x00000004u)
#define CSL_CHIP_CGFHPI_NMUX_SHIFT (0x00000002u)
#define CSL_CHIP_CGFHPI_NMUX_RESETVAL (0x00000000u)
/**----NMUX Tokens----*/
#define CSL_CHIP_CGFHPI_NMUX_NOTSET (0x00000000u)
#define CSL_CHIP_CGFHPI_NMUX_SET (0x00000001u)
#define CSL_CHIP_CGFHPI_PAGEM_MASK (0x00000002u)
#define CSL_CHIP_CGFHPI_PAGEM_SHIFT (0x00000001u)
#define CSL_CHIP_CGFHPI_PAGEM_RESETVAL (0x00000000u)
/**----PAGEM Tokens----*/
#define CSL_CHIP_CGFHPI_PAGEM_VBUS_NOT_OVRRIDE (0x00000000u)
#define CSL_CHIP_CGFHPI_PAGEM_VBUS_OVRRIDE (0x00000001u)
#define CSL_CHIP_CGFHPI_ENA_MASK (0x00000001u)
#define CSL_CHIP_CGFHPI_ENA_SHIFT (0x00000000u)
#define CSL_CHIP_CGFHPI_ENA_RESETVAL (0x00000000u)
/**----ENA Tokens----*/
#define CSL_CHIP_CGFHPI_ENA_HPI_NONFUNC (0x00000000u)
#define CSL_CHIP_CGFHPI_ENA_HPI_FUNC (0x00000001u)
#define CSL_CHIP_CGFHPI_RESETVAL (0x00000000u)
/** CFGHPIAMSB - CFGHPIAMSB Register */
#define CSL_CHIP_CFGHPIAMSB_HPIAMSB_MASK (0x000000FFu)
#define CSL_CHIP_CFGHPIAMSB_HPIAMSB_SHIFT (0x00000000u)
#define CSL_CHIP_CFGHPIAMSB_HPIAMSB_RESETVAL (0x00000000u)
#define CSL_CHIP_CFGHPIAMSB_RESETVAL (0x00000000u)
/** CFGHPIAUMB - CFGHPIAUMB Register */
#define CSL_CHIP_CFGHPIAUMB_HPIAUMB_MASK (0x000000FFu)
#define CSL_CHIP_CFGHPIAUMB_HPIAUMB_SHIFT (0x00000000u)
#define CSL_CHIP_CFGHPIAUMB_HPIAUMB_RESETVAL (0x00000000u)
#define CSL_CHIP_CFGHPIAUMB_RESETVAL (0x00000000u)
/** CGFRTI - CFGRTI Register */
#define CSL_CHIP_CGFRTI_CAPSEL1_MASK (0x00000070u)
#define CSL_CHIP_CGFRTI_CAPSEL1_SHIFT (0x00000004u)
#define CSL_CHIP_CGFRTI_CAPSEL1_RESETVAL (0x00000000u)
/**----CAPSEL1 Tokens----*/
#define CSL_CHIP_CGFRTI_CAPSEL1_MCASP0_TX (0x00000000u)
#define CSL_CHIP_CGFRTI_CAPSEL1_MCASP0_RX (0x00000001u)
#define CSL_CHIP_CGFRTI_CAPSEL1_MCASP1_TX (0x00000010u)
#define CSL_CHIP_CGFRTI_CAPSEL1_MCASP1_RX (0x00000011u)
#define CSL_CHIP_CGFRTI_CAPSEL1_MCASP2_TX (0x00000100u)
#define CSL_CHIP_CGFRTI_CAPSEL1_MCASP2_RX (0x00000101u)
#define CSL_CHIP_CGFRTI_CAPSEL0_MASK (0x00000007u)
#define CSL_CHIP_CGFRTI_CAPSEL0_SHIFT (0x00000000u)
#define CSL_CHIP_CGFRTI_CAPSEL0_RESETVAL (0x00000000u)
/**----CAPSEL0 Tokens----*/
#define CSL_CHIP_CGFRTI_CAPSEL0_MCASP0_TX (0x00000000u)
#define CSL_CHIP_CGFRTI_CAPSEL0_MCASP0_RX (0x00000001u)
#define CSL_CHIP_CGFRTI_CAPSEL0_MCASP1_TX (0x00000010u)
#define CSL_CHIP_CGFRTI_CAPSEL0_MCASP1_RX (0x00000011u)
#define CSL_CHIP_CGFRTI_CAPSEL0_MCASP2_TX (0x00000100u)
#define CSL_CHIP_CGFRTI_CAPSEL0_MCASP2_RX (0x00000101u)
#define CSL_CHIP_CGFRTI_RESETVAL (0x00000000u)
/** CGFMCASP0 - CFGMCASP0 Register */
#define CSL_CHIP_CGFMCASP0_AMUTEIN0_MASK (0x00000007u)
#define CSL_CHIP_CGFMCASP0_AMUTEIN0_SHIFT (0x00000000u)
#define CSL_CHIP_CGFMCASP0_AMUTEIN0_RESETVAL (0x00000000u)
/**----AMUTEIN0 Tokens----*/
#define CSL_CHIP_CGFMCASP0_AMUTEIN0_ZERO (0x00000000u)
#define CSL_CHIP_CGFMCASP0_AMUTEIN0_AXR07 (0x00000001u)
#define CSL_CHIP_CGFMCASP0_AMUTEIN0_AXR08/AXR15 (0x00000010u)
#define CSL_CHIP_CGFMCASP0_AMUTEIN0_AXR09/AXR14 (0x00000011u)
#define CSL_CHIP_CGFMCASP0_AMUTEIN0_AHCLKR2 (0x00000100u)
#define CSL_CHIP_CGFMCASP0_AMUTEIN0_SPI0SOM (0x00000101u)
#define CSL_CHIP_CGFMCASP0_AMUTEIN0_SPI0SCS/SCL1 (0x00000110u)
#define CSL_CHIP_CGFMCASP0_AMUTEIN0_SPI0ENA/SDA1 (0x00000111u)
#define CSL_CHIP_CGFMCASP0_RESETVAL (0x00000000u)
/** CGFMCASP1 - CFGMCASP1 Register */
#define CSL_CHIP_CGFMCASP1_AMUTEIN1_MASK (0x00000007u)
#define CSL_CHIP_CGFMCASP1_AMUTEIN1_SHIFT (0x00000000u)
#define CSL_CHIP_CGFMCASP1_AMUTEIN1_RESETVAL (0x00000000u)
/**----AMUTEIN1 Tokens----*/
#define CSL_CHIP_CGFMCASP1_AMUTEIN1_ZERO (0x00000000u)
#define CSL_CHIP_CGFMCASP1_AMUTEIN1_AXR07 (0x00000001u)
#define CSL_CHIP_CGFMCASP1_AMUTEIN1_AXR08/AXR15 (0x00000010u)
#define CSL_CHIP_CGFMCASP1_AMUTEIN1_AXR09/AXR14 (0x00000011u)
#define CSL_CHIP_CGFMCASP1_AMUTEIN1_AHCLKR2 (0x00000100u)
#define CSL_CHIP_CGFMCASP1_AMUTEIN1_SPI0SOM (0x00000101u)
#define CSL_CHIP_CGFMCASP1_AMUTEIN1_SPI0SCS/SCL1 (0x00000110u)
#define CSL_CHIP_CGFMCASP1_AMUTEIN1_SPI0ENA/SDA1 (0x00000111u)
#define CSL_CHIP_CGFMCASP1_RESETVAL (0x00000000u)
/** CGFMCASP2 - CFGMCASP2 Register */
#define CSL_CHIP_CGFMCASP2_AMUTEIN2_MASK (0x00000007u)
#define CSL_CHIP_CGFMCASP2_AMUTEIN2_SHIFT (0x00000000u)
#define CSL_CHIP_CGFMCASP2_AMUTEIN2_RESETVAL (0x00000000u)
/**----AMUTEIN2 Tokens----*/
#define CSL_CHIP_CGFMCASP2_AMUTEIN2_ZERO (0x00000000u)
#define CSL_CHIP_CGFMCASP2_AMUTEIN2_AXR07 (0x00000001u)
#define CSL_CHIP_CGFMCASP2_AMUTEIN2_AXR08/AXR15 (0x00000010u)
#define CSL_CHIP_CGFMCASP2_AMUTEIN2_AXR09/AXR14 (0x00000011u)
#define CSL_CHIP_CGFMCASP2_AMUTEIN2_AHCLKR2 (0x00000100u)
#define CSL_CHIP_CGFMCASP2_AMUTEIN2_SPI0SOM (0x00000101u)
#define CSL_CHIP_CGFMCASP2_AMUTEIN2_SPI0SCS/SCL1 (0x00000110u)
#define CSL_CHIP_CGFMCASP2_AMUTEIN2_SPI0ENA/SDA1 (0x00000111u)
#define CSL_CHIP_CGFMCASP2_RESETVAL (0x00000000u)
/** IDREG - IDREG Register */
#define CSL_CHIP_IDREG_REVISION_MASK (0xF0000000u)
#define CSL_CHIP_IDREG_REVISION_SHIFT (0x0000001Cu)
#define CSL_CHIP_IDREG_REVISION_RESETVAL (0x00000000u)
/**----REVISION Tokens----*/
#define CSL_CHIP_IDREG_REVISION_1_XX (0x00000000u)
#define CSL_CHIP_IDREG_REVISION_2_XX (0x00000001u)
#define CSL_CHIP_IDREG_ID_MASK (0x0FFFFFFFu)
#define CSL_CHIP_IDREG_ID_SHIFT (0x00000000u)
#define CSL_CHIP_IDREG_ID_RESETVAL (0x0B6AB02Fu)
#define CSL_CHIP_IDREG_RESETVAL (0x0B6AB02Fu)
/** CGFBRIDGE - CGFBRIDGE Register */
#define CSL_CHIP_CGFBRIDGE_CSPRST_MASK (0x00000001u)
#define CSL_CHIP_CGFBRIDGE_CSPRST_SHIFT (0x00000000u)
#define CSL_CHIP_CGFBRIDGE_CSPRST_RESETVAL (0x00000000u)
/**----CSPRST Tokens----*/
#define CSL_CHIP_CGFBRIDGE_CSPRST_NO_RST (0x00000000u)
#define CSL_CHIP_CGFBRIDGE_CSPRST_RST (0x00000001u)
#define CSL_CHIP_CGFBRIDGE_RESETVAL (0x00000000u)
/** DFT_read_write - DFT_read_write Register */
#define CSL_CHIP_DFT_READ_WRITE_DFT_WRITE_BRT_MASK (0x00000008u)
#define CSL_CHIP_DFT_READ_WRITE_DFT_WRITE_BRT_SHIFT (0x00000003u)
#define CSL_CHIP_DFT_READ_WRITE_DFT_WRITE_BRT_RESETVAL (0x00000000u)
#define CSL_CHIP_DFT_READ_WRITE_DFT_READ_BRT_MASK (0x00000004u)
#define CSL_CHIP_DFT_READ_WRITE_DFT_READ_BRT_SHIFT (0x00000002u)
#define CSL_CHIP_DFT_READ_WRITE_DFT_READ_BRT_RESETVAL (0x00000000u)
#define CSL_CHIP_DFT_READ_WRITE_DFT_WRITE_MVTE_MASK (0x00000002u)
#define CSL_CHIP_DFT_READ_WRITE_DFT_WRITE_MVTE_SHIFT (0x00000001u)
#define CSL_CHIP_DFT_READ_WRITE_DFT_WRITE_MVTE_RESETVAL (0x00000000u)
#define CSL_CHIP_DFT_READ_WRITE_DFT_READ_MVTE_MASK (0x00000001u)
#define CSL_CHIP_DFT_READ_WRITE_DFT_READ_MVTE_SHIFT (0x00000000u)
#define CSL_CHIP_DFT_READ_WRITE_DFT_READ_MVTE_RESETVAL (0x00000000u)
#define CSL_CHIP_DFT_READ_WRITE_RESETVAL (0x00000000u)
/***************************************************************************\
* Field Definition Macros for non memory mapped registers
\**************************************************************************/
/*******************************************************************************\
* _____________________
* | |
* | A M R |
* |___________________|
*
* AMR - addressing mode register
*
* FIELDS (msb -> lsb)
* (rw) BK1
* (rw) BK0
* (rw) B7MODE
* (rw) B6MODE
* (rw) B5MODE
* (rw) B4MODE
* (rw) A7MODE
* (rw) A6MODE
* (rw) A5MODE
* (rw) A4MODE
*
\******************************************************************************/
#define CSL_CHIP_AMR_BK1_MASK (0x3E00000u)
#define CSL_CHIP_AMR_BK1_SHIFT (0x15u)
#define CSL_CHIP_AMR_BK1_RESETVAL (0x0u)
#define CSL_CHIP_AMR_BK0_MASK (0x1F0000u)
#define CSL_CHIP_AMR_BK0_SHIFT (0x10u)
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