cslr_emif.h

基于ti tms320c672x下音频开发例子程式

#define CSL_EMIF_A2CR_R_HOLD_SHIFT       (0x00000004u)
#define CSL_EMIF_A2CR_R_HOLD_RESETVAL    (0x00000007u)

#define CSL_EMIF_A2CR_TA_MASK            (0x0000000Cu)
#define CSL_EMIF_A2CR_TA_SHIFT           (0x00000002u)
#define CSL_EMIF_A2CR_TA_RESETVAL        (0x00000003u)

#define CSL_EMIF_A2CR_ASIZE_MASK         (0x00000003u)
#define CSL_EMIF_A2CR_ASIZE_SHIFT        (0x00000000u)
#define CSL_EMIF_A2CR_ASIZE_RESETVAL     (0x00000000u)

/*----ASIZE Tokens----*/
#define CSL_EMIF_A2CR_ASIZE_8_BIT        (0x00000000u)
#define CSL_EMIF_A2CR_ASIZE_16_BIT       (0x00000001u)
#define CSL_EMIF_A2CR_ASIZE_32_BIT       (0x00000002u)

#define CSL_EMIF_A2CR_RESETVAL           (0x3FFFFFFCu)

/* A3CR */

#define CSL_EMIF_A3CR_SS_MASK            (0x80000000u)
#define CSL_EMIF_A3CR_SS_SHIFT           (0x0000001Fu)
#define CSL_EMIF_A3CR_SS_RESETVAL        (0x00000000u)

/*----SS Tokens----*/
#define CSL_EMIF_A3CR_SS_DISABLE         (0x00000000u)
#define CSL_EMIF_A3CR_SS_ENABLE          (0x00000001u)

#define CSL_EMIF_A3CR_EW_MASK            (0x40000000u)
#define CSL_EMIF_A3CR_EW_SHIFT           (0x0000001Eu)
#define CSL_EMIF_A3CR_EW_RESETVAL        (0x00000000u)

/*----EW Tokens----*/
#define CSL_EMIF_A3CR_EW_DISABLE         (0x00000000u)
#define CSL_EMIF_A3CR_EW_ENABLE          (0x00000001u)

#define CSL_EMIF_A3CR_W_SETUP_MASK       (0x3C000000u)
#define CSL_EMIF_A3CR_W_SETUP_SHIFT      (0x0000001Au)
#define CSL_EMIF_A3CR_W_SETUP_RESETVAL   (0x0000000Fu)

#define CSL_EMIF_A3CR_W_STROBE_MASK      (0x03F00000u)
#define CSL_EMIF_A3CR_W_STROBE_SHIFT     (0x00000014u)
#define CSL_EMIF_A3CR_W_STROBE_RESETVAL  (0x0000003Fu)

#define CSL_EMIF_A3CR_W_HOLD_MASK        (0x000E0000u)
#define CSL_EMIF_A3CR_W_HOLD_SHIFT       (0x00000011u)
#define CSL_EMIF_A3CR_W_HOLD_RESETVAL    (0x00000007u)

#define CSL_EMIF_A3CR_R_SETUP_MASK       (0x0001E000u)
#define CSL_EMIF_A3CR_R_SETUP_SHIFT      (0x0000000Du)
#define CSL_EMIF_A3CR_R_SETUP_RESETVAL   (0x0000000Fu)

#define CSL_EMIF_A3CR_R_STROBE_MASK      (0x00001F80u)
#define CSL_EMIF_A3CR_R_STROBE_SHIFT     (0x00000007u)
#define CSL_EMIF_A3CR_R_STROBE_RESETVAL  (0x0000003Fu)

#define CSL_EMIF_A3CR_R_HOLD_MASK        (0x00000070u)
#define CSL_EMIF_A3CR_R_HOLD_SHIFT       (0x00000004u)
#define CSL_EMIF_A3CR_R_HOLD_RESETVAL    (0x00000007u)

#define CSL_EMIF_A3CR_TA_MASK            (0x0000000Cu)
#define CSL_EMIF_A3CR_TA_SHIFT           (0x00000002u)
#define CSL_EMIF_A3CR_TA_RESETVAL        (0x00000003u)

#define CSL_EMIF_A3CR_ASIZE_MASK         (0x00000003u)
#define CSL_EMIF_A3CR_ASIZE_SHIFT        (0x00000000u)
#define CSL_EMIF_A3CR_ASIZE_RESETVAL     (0x00000000u)

/*----ASIZE Tokens----*/
#define CSL_EMIF_A3CR_ASIZE_8_BIT        (0x00000000u)
#define CSL_EMIF_A3CR_ASIZE_16_BIT       (0x00000001u)
#define CSL_EMIF_A3CR_ASIZE_32_BIT       (0x00000002u)

#define CSL_EMIF_A3CR_RESETVAL           (0x3FFFFFFCu)

/* A4CR */

#define CSL_EMIF_A4CR_SS_MASK            (0x80000000u)
#define CSL_EMIF_A4CR_SS_SHIFT           (0x0000001Fu)
#define CSL_EMIF_A4CR_SS_RESETVAL        (0x00000000u)

/*----SS Tokens----*/
#define CSL_EMIF_A4CR_SS_DISABLE         (0x00000000u)
#define CSL_EMIF_A4CR_SS_ENABLE          (0x00000001u)

#define CSL_EMIF_A4CR_EW_MASK            (0x40000000u)
#define CSL_EMIF_A4CR_EW_SHIFT           (0x0000001Eu)
#define CSL_EMIF_A4CR_EW_RESETVAL        (0x00000000u)

/*----EW Tokens----*/
#define CSL_EMIF_A4CR_EW_DISABLE         (0x00000000u)
#define CSL_EMIF_A4CR_EW_ENABLE          (0x00000001u)

#define CSL_EMIF_A4CR_W_SETUP_MASK       (0x3C000000u)
#define CSL_EMIF_A4CR_W_SETUP_SHIFT      (0x0000001Au)
#define CSL_EMIF_A4CR_W_SETUP_RESETVAL   (0x0000000Fu)

#define CSL_EMIF_A4CR_W_STROBE_MASK      (0x03F00000u)
#define CSL_EMIF_A4CR_W_STROBE_SHIFT     (0x00000014u)
#define CSL_EMIF_A4CR_W_STROBE_RESETVAL  (0x0000003Fu)

#define CSL_EMIF_A4CR_W_HOLD_MASK        (0x000E0000u)
#define CSL_EMIF_A4CR_W_HOLD_SHIFT       (0x00000011u)
#define CSL_EMIF_A4CR_W_HOLD_RESETVAL    (0x00000007u)

#define CSL_EMIF_A4CR_R_SETUP_MASK       (0x0001E000u)
#define CSL_EMIF_A4CR_R_SETUP_SHIFT      (0x0000000Du)
#define CSL_EMIF_A4CR_R_SETUP_RESETVAL   (0x0000000Fu)

#define CSL_EMIF_A4CR_R_STROBE_MASK      (0x00001F80u)
#define CSL_EMIF_A4CR_R_STROBE_SHIFT     (0x00000007u)
#define CSL_EMIF_A4CR_R_STROBE_RESETVAL  (0x0000003Fu)

#define CSL_EMIF_A4CR_R_HOLD_MASK        (0x00000070u)
#define CSL_EMIF_A4CR_R_HOLD_SHIFT       (0x00000004u)
#define CSL_EMIF_A4CR_R_HOLD_RESETVAL    (0x00000007u)

#define CSL_EMIF_A4CR_TA_MASK            (0x0000000Cu)
#define CSL_EMIF_A4CR_TA_SHIFT           (0x00000002u)
#define CSL_EMIF_A4CR_TA_RESETVAL        (0x00000003u)

#define CSL_EMIF_A4CR_ASIZE_MASK         (0x00000003u)
#define CSL_EMIF_A4CR_ASIZE_SHIFT        (0x00000000u)
#define CSL_EMIF_A4CR_ASIZE_RESETVAL     (0x00000000u)

/*----ASIZE Tokens----*/
#define CSL_EMIF_A4CR_ASIZE_8_BIT        (0x00000000u)
#define CSL_EMIF_A4CR_ASIZE_16_BIT       (0x00000001u)
#define CSL_EMIF_A4CR_ASIZE_32_BIT       (0x00000002u)

#define CSL_EMIF_A4CR_RESETVAL           (0x3FFFFFFCu)

/* SDTIMR */

#define CSL_EMIF_SDTIMR_T_RFC_MASK       (0xF8000000u)
#define CSL_EMIF_SDTIMR_T_RFC_SHIFT      (0x0000001Bu)
#define CSL_EMIF_SDTIMR_T_RFC_RESETVAL   (0x00000000u)

#define CSL_EMIF_SDTIMR_T_RP_MASK        (0x07000000u)
#define CSL_EMIF_SDTIMR_T_RP_SHIFT       (0x00000018u)
#define CSL_EMIF_SDTIMR_T_RP_RESETVAL    (0x00000000u)

#define CSL_EMIF_SDTIMR_T_RCD_MASK       (0x00700000u)
#define CSL_EMIF_SDTIMR_T_RCD_SHIFT      (0x00000014u)
#define CSL_EMIF_SDTIMR_T_RCD_RESETVAL   (0x00000002u)

#define CSL_EMIF_SDTIMR_T_WR_MASK        (0x00070000u)
#define CSL_EMIF_SDTIMR_T_WR_SHIFT       (0x00000010u)
#define CSL_EMIF_SDTIMR_T_WR_RESETVAL    (0x00000001u)

#define CSL_EMIF_SDTIMR_T_RAS_MASK       (0x0000F000u)
#define CSL_EMIF_SDTIMR_T_RAS_SHIFT      (0x0000000Cu)
#define CSL_EMIF_SDTIMR_T_RAS_RESETVAL   (0x0000000Cu)

#define CSL_EMIF_SDTIMR_T_RC_MASK        (0x00000F00u)
#define CSL_EMIF_SDTIMR_T_RC_SHIFT       (0x00000008u)
#define CSL_EMIF_SDTIMR_T_RC_RESETVAL    (0x0000000Fu)

#define CSL_EMIF_SDTIMR_T_RRD_MASK       (0x00000070u)
#define CSL_EMIF_SDTIMR_T_RRD_SHIFT      (0x00000004u)
#define CSL_EMIF_SDTIMR_T_RRD_RESETVAL   (0x00000000u)

#define CSL_EMIF_SDTIMR_RESETVAL         (0x0021CF00u)

/* SDSRETR */

#define CSL_EMIF_SDSRETR_T_XS_MASK       (0x0000001Fu)
#define CSL_EMIF_SDSRETR_T_XS_SHIFT      (0x00000000u)
#define CSL_EMIF_SDSRETR_T_XS_RESETVAL   (0x00000019u)

#define CSL_EMIF_SDSRETR_RESETVAL        (0x00000019u)

/* EIRR */

#define CSL_EMIF_EIRR_AT_MASK            (0x00000001u)
#define CSL_EMIF_EIRR_AT_SHIFT           (0x00000000u)
#define CSL_EMIF_EIRR_AT_RESETVAL        (0x00000000u)

/*----AT Tokens----*/
#define CSL_EMIF_EIRR_AT_NOT_OCCURED     (0x00000000u)
#define CSL_EMIF_EIRR_AT_OCCURED         (0x00000001u)

#define CSL_EMIF_EIRR_RESETVAL           (0x00000000u)

/* EIMR */

#define CSL_EMIF_EIMR_ATM_MASK           (0x00000001u)
#define CSL_EMIF_EIMR_ATM_SHIFT          (0x00000000u)
#define CSL_EMIF_EIMR_ATM_RESETVAL       (0x00000000u)

/*----ATM Tokens----*/
#define CSL_EMIF_EIMR_ATM_NOT_OCCURED    (0x00000000u)
#define CSL_EMIF_EIMR_ATM_OCCURED        (0x00000001u)

#define CSL_EMIF_EIMR_RESETVAL           (0x00000000u)

/* EIMSR */

#define CSL_EMIF_EIMSR_ATMSET_MASK       (0x00000001u)
#define CSL_EMIF_EIMSR_ATMSET_SHIFT      (0x00000000u)
#define CSL_EMIF_EIMSR_ATMSET_RESETVAL   (0x00000000u)

/*----ATMSET Tokens----*/
#define CSL_EMIF_EIMSR_ATMSET_DISABLE    (0x00000000u)
#define CSL_EMIF_EIMSR_ATMSET_ENABLE     (0x00000001u)

#define CSL_EMIF_EIMSR_RESETVAL          (0x00000000u)

/* EIMCR */

#define CSL_EMIF_EIMCR_ATMCLR_MASK       (0x00000001u)
#define CSL_EMIF_EIMCR_ATMCLR_SHIFT      (0x00000000u)
#define CSL_EMIF_EIMCR_ATMCLR_RESETVAL   (0x00000000u)

#define CSL_EMIF_EIMCR_RESETVAL          (0x00000000u)

#endif