📄 initaic10.asm
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BC FSC4Sec1, ALT ; yes: next 2ndary comm cycle
NOP ; no: finish
STM SPCR1, McBSP0_SPSA ; disable McBSP0 RX
LDM McBSP0_SPSD,A
AND #0xFFFE, A
STLM A, McBSP0_SPSD
STM SPCR2, McBSP0_SPSA ; disable McBSP0 TX
LDM McBSP0_SPSD,A
AND #0xFFFE, A
STLM A, McBSP0_SPSD
RPT #5
NOP
NOP
******************************************************************************
******* Use McBSP0 to Initalize all AIC Control Registers *******
******* -- AIC10 Configuration *******
******************************************************************************
NOP
ST #0x0004, CRegCount ; set AIC control reg counter (4 CRs)
NOP
STM SPCR2, McBSP0_SPSA ; enable McBSP0 Tx
LDM McBSP0_SPSD, A ; (by setting bit0 at SPCR2)
OR #0x0001, A
STLM A, McBSP0_SPSD
NOP
NOP
STM #0x0020, IMR ; unmask DXINT0 for 'IDLE'
******* Load Sencondary Comm Phase Configuring AIC10 CRs *******
******* Note: DX = [(AIC ID) 0 (CR #) x |Config]
******* [ 15 ~ 13 12 11~9 8 | 7 ~ 0]
*******
NOP ; contents for configuring CR1
STM #WriteMCR1, AR1
STM #WriteSCR1, AR2
LD AIC10Num, A ; set FSCount
STL A, FSCount
BD InitStart
NOP
NOP
InitAICR2:
NOP ; contents for configuring CR2
LD CRegCount, A
SUB #3, A
BC InitAICR3, ALT
NOP
NOP
STM #WriteMCR2, AR1
STM #WriteSCR2, AR2
LD AIC10Num, A ; set FSCount
STL A, FSCount
BD InitStart
NOP
NOP
InitAICR3:
NOP ; contents for configuring CR3
LD CRegCount, A
SUB #2, A
BC InitAICR4, ALT
NOP
NOP
STM #WriteMCR3, AR1
STM #WriteSCR3, AR2
LD AIC10Num, A ; set FSCount
STL A, FSCount
BD InitStart
NOP
NOP
InitAICR4:
NOP ; contents for configuring CR4
STM #WriteMCR4, AR1
STM #WriteSCR4, AR2
LD AIC10Num, A ; set FSCount
STL A, FSCount
NOP
NOP
InitStart:
NOP ; this is a primary cycle
STM #0x3FFF, IFR ; Clear interrupt flag
STM #SECRequ,McBSP0_DXR1 ; load 2nd req to DX (at primary)
IDLE 1 ; wait for the TX finished
LD FSCount, A ; check if all AIC are requested
SUB #1, A
STL A, FSCount
BC InitStart, AGT ; no: back to do more request
NOP ; yes: to 2ndary cycle
******* Configuring Master AIC10 *******
NOP
LD AIC10Num, A ; get master AIC ID from Ident
SUB #1, A ; ID = (AIC10Num-1) << 13
SFTA A, 13, A
LDM AR1, B ; get CRx for master
OR B, A ; ID.OR.CRx, configuring contents
STM #0x3FFF, IFR ; Clear interrupt flag
STLM A, McBSP0_DXR1 ; put config data to CRx
IDLE 1 ; wait for the TX finished
ST #1, FSCount ; clear frame sync counter
******* Configuring Slave AIC10(s) *******
InitAICSec:
NOP
ADDM #1, FSCount ; increase FSCount
LD FSCount, A ; check if FSCount > AIC10Num
SUB AIC10Num, A
BC InitAICSec1, AGT ; yes: to next CRs
NOP ; no:
NOP
LD AIC10Num, A ; get master AIC ID from Ident
SUB FSCount, A ; ID = (AIC10Num-FSCount) << 13
SFTA A, 13, A
LDM AR2, B ; get CRx for slave
OR B, A ; ID.OR.CRx, configuring contents
STM #0x3FFF, IFR ; Clear interrupt flag
STLM A, McBSP0_DXR1 ; put config data to CRx
IDLE 1 ; wait for the TX finished
NOP
BD InitAICSec ; to next slave
NOP
NOP
InitAICSec1: ; check if all 4 CRs have been conf
NOP
LD CRegCount, A
SUB #1, A
STL A, CRegCount
BC InitAICR2, AGT
NOP
NOP
******************************************************************************
******* InitAIC10 Return to Main Routine *******
******************************************************************************
InitFinish:
NOP
STM SPCR1, McBSP0_SPSA ; disable McBSP0 RX
LDM McBSP0_SPSD,A
AND #0xFFFE, A
STLM A, McBSP0_SPSD
STM SPCR2, McBSP0_SPSA ; disable McBSP0 TX
LDM McBSP0_SPSD,A
AND #0xFFFE, A
STLM A, McBSP0_SPSD
RPT #7
NOP
STM 0x0000, IMR ; disable peripheral interrupts
STM #0x3FFF, IFR ; reset all interrupt flags
CALL ReadCRs ; read & store AIC10's CRs status
NOP
* STM #0x0010, IMR ; enable BRINT0 interrupts
* STM #0x0800, IMR ; enable BXINT1 interrupts
STM #0x3FFF, IFR ; reset all interrupt flags
RSBX INTM ; enable system interrupts
STM SPCR1, McBSP0_SPSA ; ena McBSP0 RX for ADC data in
LDM McBSP0_SPSD,A
OR #0x0001, A
STLM A, McBSP0_SPSD
STM SPCR2, McBSP0_SPSA ; enable McBSP0 TX for DTMF out
LDM McBSP0_SPSD,A
OR #0x0001, A
STLM A, McBSP0_SPSD
LDM TCR, A ; start timer0 for main loop
AND #0xFFEF, A ; (by clear bit4 of TCR)
STLM A, TCR
ST #0, LoopCount ; reset main loop counter
NOP
RETD ; return to main
NOP
NOP
************************************************************************
** Local Subrotuines
************************************************************************
******* Waiting for McBSP0 RX Finished *******
IfRxRDY0:
NOP
STM SPCR1, McBSP0_SPSA ; enable McBSP0 Rx
LDM McBSP0_SPSD, A
AND #0002h, A ; mask RRDY bit
BC IfRxRDY0, AEQ ; keep checking
RETD ; return
NOP
NOP
******* Waiting for McBSP0 TX Finished *******
IfTxRDY0:
NOP
STM SPCR2, McBSP0_SPSA ; enable McBSP0 Tx
LDM McBSP0_SPSD, A
AND #0002h, A ; mask TRDY bit
BC IfTxRDY0, AEQ ; keep checking
RETD ; return
NOP
NOP
******* Read & Store AIC10 Control Register Values After Config *******
ReadCRs:
NOP
STM SPCR1, McBSP0_SPSA ; ena McBSP0 RX for ADC data in
LDM McBSP0_SPSD,A
OR #0x0001, A
STLM A, McBSP0_SPSD
STM SPCR2, McBSP0_SPSA ; enable McBSP0 TX for DTMF out
LDM McBSP0_SPSD,A
OR #0x0001, A
STLM A, McBSP0_SPSD
LD #InitVari, DP ; load data page
RPT #7
NOP
STM #0x0001, McBSP0_DXR1
CALL IfTxRDY0 ; wait for Tx from McBSP0 finished
CALL IfRxRDY0 ; also check Rx get a data
LDM McBSP0_DRR1, A ; ld Rx data to regA & clr RRDY flag
STM #0x0001, McBSP0_DXR1
CALL IfTxRDY0
CALL IfRxRDY0 ; also check Rx get a data
LDM McBSP0_DRR1, A ; ld Rx data to regA & clr RRDY flag
STM #0x3200, McBSP0_DXR1 ; set to request read master AIC CR1
CALL IfTxRDY0 ; wait for Tx from McBSP0 finished
CALL IfRxRDY0 ; also check Rx get a data
LDM McBSP0_DRR1, A ; ld Rx data to regA & clr RRDY flag
STL A, MstCR1 ; save master CR1 to MstCR4
STM #0x1200, McBSP0_DXR1 ; set to request read slave AIC CR1
CALL IfTxRDY0 ; wait for Tx from McBSP0 finished
CALL IfRxRDY0 ; also check Rx get a data
LDM McBSP0_DRR1, A ; ld Rx data to regA & clr RRDY flag
STL A, SlvCR1 ; save master CR1 to SlvCR4
NOP
STM #0x0001, McBSP0_DXR1
CALL IfTxRDY0 ; wait for Tx from McBSP0 finished
CALL IfRxRDY0 ; also check Rx get a data
LDM McBSP0_DRR1, A ; ld Rx data to regA & clr RRDY flag
STM #0x0001, McBSP0_DXR1
CALL IfTxRDY0
CALL IfRxRDY0 ; also check Rx get a data
LDM McBSP0_DRR1, A ; ld Rx data to regA & clr RRDY flag
STM #0x3400, McBSP0_DXR1 ; set to request read master AIC CR1
CALL IfTxRDY0 ; wait for Tx from McBSP0 finished
CALL IfRxRDY0 ; also check Rx get a data
LDM McBSP0_DRR1, A ; ld Rx data to regA & clr RRDY flag
STL A, MstCR2 ; save master CR1 to MstCR4
STM #0x1400, McBSP0_DXR1 ; set to request read slave AIC CR1
CALL IfTxRDY0 ; wait for Tx from McBSP0 finished
CALL IfRxRDY0 ; also check Rx get a data
LDM McBSP0_DRR1, A ; ld Rx data to regA & clr RRDY flag
STL A, SlvCR2 ; save master CR1 to SlvCR4
NOP
STM #0x0001, McBSP0_DXR1
CALL IfTxRDY0 ; wait for Tx from McBSP0 finished
CALL IfRxRDY0 ; also check Rx get a data
LDM McBSP0_DRR1, A ; ld Rx data to regA & clr RRDY flag
STM #0x0001, McBSP0_DXR1
CALL IfTxRDY0
CALL IfRxRDY0 ; also check Rx get a data
LDM McBSP0_DRR1, A ; ld Rx data to regA & clr RRDY flag
STM #0x3600, McBSP0_DXR1 ; set to request read master AIC CR1
CALL IfTxRDY0 ; wait for Tx from McBSP0 finished
CALL IfRxRDY0 ; also check Rx get a data
LDM McBSP0_DRR1, A ; ld Rx data to regA & clr RRDY flag
STL A, MstCR3 ; save master CR1 to MstCR4
STM #0x1600, McBSP0_DXR1 ; set to request read slave AIC CR1
CALL IfTxRDY0 ; wait for Tx from McBSP0 finished
CALL IfRxRDY0 ; also check Rx get a data
LDM McBSP0_DRR1, A ; ld Rx data to regA & clr RRDY flag
STL A, SlvCR3 ; save master CR1 to SlvCR4
NOP
STM #0x0001, McBSP0_DXR1
CALL IfTxRDY0 ; wait for Tx from McBSP0 finished
CALL IfRxRDY0 ; also check Rx get a data
LDM McBSP0_DRR1, A ; ld Rx data to regA & clr RRDY flag
STM #0x0001, McBSP0_DXR1
CALL IfTxRDY0
CALL IfRxRDY0 ; also check Rx get a data
LDM McBSP0_DRR1, A ; ld Rx data to regA & clr RRDY flag
STM #0x3800, McBSP0_DXR1 ; set to request read master AIC CR1
CALL IfTxRDY0 ; wait for Tx from McBSP0 finished
CALL IfRxRDY0 ; also check Rx get a data
LDM McBSP0_DRR1, A ; ld Rx data to regA & clr RRDY flag
STL A, MstCR4 ; save master CR1 to MstCR4
STM #0x1800, McBSP0_DXR1 ; set to request read slave AIC CR1
CALL IfTxRDY0 ; wait for Tx from McBSP0 finished
CALL IfRxRDY0 ; also check Rx get a data
LDM McBSP0_DRR1, A ; ld Rx data to regA & clr RRDY flag
STL A, SlvCR4 ; save master CR1 to SlvCR4
NOP
STM SPCR1, McBSP0_SPSA ; disable McBSP0 RX
LDM McBSP0_SPSD,A
AND #0xFFFE, A
STLM A, McBSP0_SPSD
STM SPCR2, McBSP0_SPSA ; disable McBSP0 TX
LDM McBSP0_SPSD,A
AND #0xFFFE, A
STLM A, McBSP0_SPSD
RPT #7
NOP
RET
NOP
.end
************************************************************************
** End of File -- InitAIC10.asm
************************************************************************
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