mplinitshutdown.c

NATIONAL公司DP83816芯片Linux下驱动

   ENTER(MplMacReset);

   // Disable the adapter
   disableDevice(pMplCtx);

   // Pull reset, wait (total 10 msec) and check for completion
   MPL_WRITE32(pMplCtx, CR, SOFTRESET);
   OaiSleep(RESETINTERVAL_MAC);
   for (i = 0x0; (i < 10) && (MPL_READ32(pMplCtx, CR) & SOFTRESET); i++)
   {
      OaiSleep(RESETINTERVAL_MAC);
   }

   if ((MPL_READ32(pMplCtx, CR) & SOFTRESET))
   {
      EXIT(MplMacReset);
      return NS_STATUS_HARDWARE_FAILURE; // device failed to flag completion
   }

#ifndef MPL_NO_EEPROM
   // Reload defaults from EEPROM, wait (total 10 msec) and check for completion
   MPL_WRITE32(pMplCtx, MTSCR, MPL_READ32(pMplCtx, MTSCR) | EELOAD_EN);
   OaiSleep(EELOADINTERVAL);
   for (i = 0x0; (i < 10) && (MPL_READ32(pMplCtx, MTSCR) & EELOAD_EN); i++)
   {
      OaiSleep(EELOADINTERVAL);
   }

   if ((MPL_READ32(pMplCtx, MTSCR) & EELOAD_EN))
   {
      EXIT(MplMacReset);
      MPL_TRACE(("Warning : EEPROM Load did not complete \n"));

      // Get the MAC address from the EEPROM and set on MAC manually
      // This will atleast get us going...
      MplGetMacAddress(pMplCtx, NS_TRUE, pMplCtx->permMacAddr);
      MplSetMacAddress(pMplCtx, pMplCtx->permMacAddr);
   }
#endif// MPL_NO_EEPROM

   // Get the permanent MAC address and store it away
   MplGetMacAddress(pMplHandle, NS_FALSE, pMplCtx->permMacAddr);

   EXIT(MplMacReset);
   return NS_STATUS_SUCCESS;
}

//*****************************************************************************
//   MplCfgMTU
//      Configures the maximum packet size supported by MPL
//
//   Parameters
//      pMplHandle
//         MPL device handle returned following a call to MplInitialize
//      mtu
//         The maximum packet size queued for transmission or reception
//
//   Return Value
//      NS_STATUS_SUCCESS
//         The requested MTU was successfully configured on the device.
//      NS_STATUS_INVALID_PARAM
//         The size is greater than the maximum supported on the device.
//
//*****************************************************************************
MPL_STATUS
   MplCfgMTU (
      IN NS_VOID  *pMplHandle,
      IN NS_UINT   mtu
      )
{
   MPL_CONTEXT *pMplCtx = (MPL_CONTEXT *)pMplHandle;
   NS_UINT32 regVal;

   ENTER(MplCfgMTU);

   // Make sure we are within limits
   if (mtu > pMplCtx->caps.txCaps.maxPacketSize)
   {
      EXIT(MplCfgMTU);
      return NS_STATUS_INVALID_PARM;
   }

   // Note the MTU in the context
   pMplCtx->mtu = mtu;

   // Enable jumbo if mtu larger than Ethernet MTU
   if (mtu > MTU_ETHERNET)
   {
      regVal = MPL_READ32(pMplCtx, RXCFG);
      regVal |= ACCEPT_LONGPKT;
      MPL_WRITE32(pMplCtx, RXCFG, regVal);
   }

   EXIT(MplCfgMTU);
   return NS_STATUS_SUCCESS;
}

//+++++ Local Functions
//#####################

//*****************************************************************************
//   setSoftRegs
//      Set the software cfg regs (i.e. reg fields maintained in the MPL 
//       context area) with either the default values or the current value
//       (by reading from the hardware cfg regs).
//
//   Parameters
//      pMplHandle
//         MPL device handle
//      valType
//         Type of value of be written (MPL_REGS_DEFAULT or MPL_REGS_CURRENT)
//
//   Return Value
//      None
//
//*****************************************************************************
NS_VOID
   setSoftRegs(
      IN NS_VOID       *pMplHandle,
      IN MPL_REGS_TYPE  valType
      )
{
   MPL_CONTEXT *pMplCtx = (MPL_CONTEXT *)pMplHandle;

   ENTER(setSoftRegs);

   // Set the soft register to default or to the current values on the device
   if (valType == MPL_REGS_DEFAULT)
   {
      // CFG Register Defaults - Respect EEPROM loaded bits and retain them
      pMplCtx->cfgReg = MPL_READ32(pMplCtx, CFG) & CFG_EEPROM_MASK;
      pMplCtx->cfgReg |= CFG_DEFAULT;
      
      // IMR Register Defaults
      pMplCtx->imrReg = IMR_DEFAULT;

      // IER Register Defaults
      pMplCtx->ierReg = IER_DEFAULT;

      // IHR Register Defaults
      pMplCtx->ihrReg = IHR_DEFAULT;

      // TXCFG Register Defaults
      pMplCtx->txCfgReg = TXCFG_DEFAULT;

      // RXCFG Register Defaults
      pMplCtx->rxCfgReg = RXCFG_DEFAULT;

      // GPIO Register Defaults- Respect EEPROM loaded bits and retain them
      pMplCtx->gpioReg = MPL_READ32(pMplCtx, GPIOR) & GPIOR_EEPROM_MASK;
      pMplCtx->gpioReg |= GPIOR_DEFAULT;

      // CCSR Register Defaults - Respect EEPROM loaded bits and retain them
      pMplCtx->ccsrReg = MPL_READ32(pMplCtx, CCSR) & CCSR_EEPROM_MASK;
      pMplCtx->ccsrReg |= CCSR_DEFAULT;

      // WCSR Register Defaults - Respect EEPROM loaded bits and retain them
      pMplCtx->wcsrReg = MPL_READ32(pMplCtx, WCSR) & WCSR_EEPROM_MASK;
      pMplCtx->wcsrReg |= WCSR_DEFAULT;

      // RFCR Register Defaults - Respect EEPROM loaded bits and retain them
      pMplCtx->rfcrReg = MPL_READ32(pMplCtx, RFCR) & RFCR_EEPROM_MASK;
      pMplCtx->rfcrReg |= RFCR_DEFAULT;

      // VRCR Register Defaults
      pMplCtx->vrcrReg = VRCR_DEFAULT;

      // VIPTCR Register Defaults
      pMplCtx->vtcrReg = VTCR_DEFAULT;

      // PQCR Register Defaults
      pMplCtx->pqcrReg = PQCR_DEFAULT;
   }
   else
   {
      // CFG Register Contents
      pMplCtx->cfgReg = MPL_READ32(pMplCtx, CFG);
      
      // IMR Register Contents
      pMplCtx->imrReg = MPL_READ32(pMplCtx, IMR);

      // IER Register Contents
      pMplCtx->ierReg= MPL_READ32(pMplCtx, IER);

      // IHR Register Contents
      pMplCtx->ihrReg = MPL_READ32(pMplCtx, IHR);

      // TXCFG Register Contents
      pMplCtx->txCfgReg = MPL_READ32(pMplCtx, TXCFG);

      // RXCFG Register Contents
      pMplCtx->rxCfgReg = MPL_READ32(pMplCtx, RXCFG);

      // GPIO Register Contents
      pMplCtx->gpioReg = MPL_READ32(pMplCtx, GPIOR);

      // CCSR Register Contents
      pMplCtx->ccsrReg = MPL_READ32(pMplCtx, CCSR);

      // WCSR Register Contents
      pMplCtx->wcsrReg = MPL_READ32(pMplCtx, WCSR);

      // RFCR Register Contents
      pMplCtx->rfcrReg = MPL_READ32(pMplCtx, RFCR) & ~RXFLTRAM_ADDRMASK;

      // PQCR Register Contents
      pMplCtx->pqcrReg =  MPL_READ32(pMplCtx, PQCR);;

      // VIPRCR Register Contents
      pMplCtx->vrcrReg = MPL_READ32(pMplCtx, VRCR);

      // VIPTCR Register Contents
      pMplCtx->vtcrReg = MPL_READ32(pMplCtx, VTCR);

      // BootROM Register Contents - Somehow seems to be altered on resume
      pMplCtx->brarReg = MPL_READ32(pMplCtx, BRAR);
   }

   EXIT(setSoftRegs);
   return;
}

//*****************************************************************************
//   setHardRegs
//      Write hardware cfg registers with current values stored in the MPL
//       context (i.e from the soft registers)
//
//   Parameters
//      pMplHandle
//         MPL device handle
//
//   Return Value
//      None
//
//*****************************************************************************
NS_VOID
   setHardRegs(
      IN NS_VOID  *pMplHandle
      )
{
   MPL_CONTEXT *pMplCtx = (MPL_CONTEXT *)pMplHandle;

   ENTER(setHardRegs);

   // CFG Register Contents
   MPL_WRITE32(pMplCtx, CFG, pMplCtx->cfgReg);
   
   // IMR Register Contents
   MPL_WRITE32(pMplCtx, IMR, pMplCtx->imrReg);

   // IER Register Contents
   MPL_WRITE32(pMplCtx, IER, pMplCtx->ierReg);

   // IHR Register Contents
   MPL_WRITE32(pMplCtx, IHR, pMplCtx->ihrReg);

   // TXCFG Register Contents
   MPL_WRITE32(pMplCtx, TXCFG, pMplCtx->txCfgReg);

   // RXCFG Register Contents
   MPL_WRITE32(pMplCtx, RXCFG, pMplCtx->rxCfgReg);

   // GPIO Register Contents
   MPL_WRITE32(pMplCtx, GPIOR, pMplCtx->gpioReg);

   // CCSR Register Contents
   // The chip could be used as a LOM device or a standalone PCI device
   //  In either case the PME bit could be enabled in the EEPROM, which
   //  would case incoming packets to be scanned only, not passed to the host 
   //  So disable PME in normal mode and set it only while WOL is being set
   MPL_WRITE32(pMplCtx, CCSR, (pMplCtx->ccsrReg & ~PMEEN));

   // WCSR Register Contents
   MPL_WRITE32(pMplCtx, WCSR, pMplCtx->wcsrReg);

   // PQCR Register Contents
   MPL_WRITE32(pMplCtx, PQCR, pMplCtx->pqcrReg);

   // VIPRCR Register Contents
   MPL_WRITE32(pMplCtx, VRCR, pMplCtx->vrcrReg);

   // VIPTCR Register Contents
   MPL_WRITE32(pMplCtx, VTCR, pMplCtx->vtcrReg);

   // BRAR Register Contents
#if 0
   // Writing to BRAR and following it with a RFCR read does not work on MP-1/2
   // So for now disable this
   // Now to start-off we should not even be saving this reg - But on Linux
   // it apprears that a suspend-resume causes this to be altered 
   MPL_WRITE32(pMplCtx, BRAR, pMplCtx->brarReg);
#endif

   // RFCR Register Contents - Disable before writing
   MPL_WRITE32(pMplCtx, RFCR, 0x0);
   MPL_WRITE32(pMplCtx, RFCR, pMplCtx->rfcrReg);

   EXIT(setHardRegs);
   return;
}

//*****************************************************************************
//   disableDevice
//      Disable the device
//
//   Parameters
//      pMplHandle
//         MPL device handle
//
//   Return Value
//      None
//
//*****************************************************************************
static 
NS_VOID
   disableDevice(
      IN NS_VOID  *pMplHandle
      )
{
   MPL_CONTEXT *pMplCtx = (MPL_CONTEXT *)pMplHandle;

   ENTER(disableDevice);

#ifdef MPL_DIAG_MODE
   if (pMplCtx->diag.mode == MPL_MODE_LOAD_ONLY)
   {
      // Nothing to do
      EXIT(disableDevice);
      return;
   }
#endif //MPL_DIAG_MODE

   // Disable adapter interrupts
   MplInterruptDisable(pMplHandle);

   // Disable all transmit and receive engines
   MPL_WRITE32(pMplCtx, CR, TX_DIS | RX_DIS);

   EXIT(disableDevice);
   return;
}