mplregdefaults.h

NATIONAL公司DP83816芯片Linux下驱动

//**********************************************************************
//
//  MPLREGDEFAULTS.H
//
//  Copyright (c) 2004 National Semiconductor Corporation.
//  All Rights Reserved
//
//  Defaults for all the configuration related registers
//
//  Note: A NSM module implementor can edit the contents of this file
//  assuming he/she know what they are doing. MPL will set bring up
//  the device with the configuration as defined here!!
// 
//**********************************************************************

#ifndef _MPLREGDEFAULTS_H_
#define _MPLREGDEFAULTS_H_

// EEPROM_MASK define the bits that are loaded from the EEPROM
//  Normally these bits are loaded as is and the defaults don't mess
//  around with these. If you have a need to modify the EEPROM defaults
//  then change the XXX_EEPROM_MASK bit definitions


// CFG Register Defaults - Includes MP1/2/3
#define CFG_EEPROM_MASK 0x03F1E801

#ifndef MPL_EXTERNAL_PHY
#define CFG_DEFAULT (ABORT_ON_EXCESSIVE_DEF | PINT_ACEN)
#else
#define CFG_DEFAULT (ABORT_ON_EXCESSIVE_DEF | PINT_ACEN | EXT_PHY)
#endif // MPL_EXTERNAL_PHY

// IMR Register Defaults - FM: Evaluate
#define IMR_DEFAULT (RXOK | RXERR | RXOVERUN | RXIDLE | \
                     TXOK | TXERR | TXUNDERRUN | \
                     MIBSTATS | PHYSTSCHANGE | SW_INT | \
                     HIORDER_INT | RXSTSFIFO_OVRN |     \
                     PCI_TARGABORT | PCI_MSTRABORT |    \
                     PCI_SERR | PCI_PARERR)

// IER Register Defaults
#define IER_DEFAULT 0x0

// IHR Register Defaults
#define HOLD_TIME 0x0a //In 100us - Default set to 1msec
#define IHR_DEFAULT (HOLD_TIME)

// TXCFG Register Defaults
#define TXFILLTHRESH    16 // 512 Bytes (In 32byte units), never be set to 0x0
#define TXDRAINTHRESH    2 // 64 Bytes (In 32byte units), never be set to 0x0
#define TXCFG_DEFAULT (EXC_COLN_RETRY | AUTOTXPAD_EN | MXDMA256 | \
                       (TXFILLTHRESH << TXFILL_SHIFT) | TXDRAINTHRESH)

// RXCFG Register Defaults
#define RXDRAINTHRESH   16 // 128 Bytes (In 8byte units)
// FM: Disable? DMA_USECACHESIZ_EN
#define RXCFG_DEFAULT (MXDMA256 | ACCEPT_CRCALIGNERR | (RXDRAINTHRESH << RXDRAIN_SHIFT))

// GPIO Register Defaults 
#define GPIOR_EEPROM_MASK 0x000003FF
#define GPIOR_DEFAULT  0x0

// CCSR Register Defaults
#define CCSR_EEPROM_MASK 0x00000100
#define CCSR_DEFAULT     (PMESTS)  //Clears olders status

// WCSR Register Defaults
#define WCSR_EEPROM_MASK 0x0000061E
#define WCSR_DEFAULT  0x0

// RFCR Register Defaults
#define RFCR_EEPROM_MASK 0xF8500000
#define RFCR_DEFAULT (ACCEPT_PERFECTMATCH | ACCEPT_ALLBCAST | RXFLTR_EN)

// PQCR Register Defaults
// Good place to define quota defaults if you need it
#define PQCR_DEFAULT  0x0

// VRCR Register Defaults
#define VRCR_DEFAULT  0x0

// VTCR Register Defaults
#define VTCR_DEFAULT  (VPAD68)

#endif // _MPLREGDEFAULTS_H_