mplregs.h

NATIONAL公司DP83816芯片Linux下驱动

#define WAKEON_PATRN5       0x00001000  // wake on pattern #5 match (R/W) 
#define WAKEON_PATRN6       0x00002000  // wake on pattern #6 match (R/W) 
#define WAKEON_PATRN7       0x00004000  // wake on pattern #7 match (R/W) 

#define WAKESTS_PATRN4      0x00020000  // pattern4 match wake event (ROSC) 
#define WAKESTS_PATRN5      0x00040000  // pattern5 match wake event (ROSC) 
#define WAKESTS_PATRN6      0x00080000  // pattern6 match wake event (ROSC) 
#define WAKESTS_PATRN7      0x00100000  // pattern7 match wake event (ROSC) 
#define WAKESTS_SEC_HACK    0x00200000  // magic pkt security hack event (ROSC)
#define WAKESTS_PHYSTSCHNG  0x00400000  // phy sts change wake event (ROSC)
#define WAKESTS_UNICAST     0x00800000  // unicast pkt wake event (ROSC) 
#define WAKESTS_MULTICAST   0x01000000  // multicast pkt wake event (ROSC) 
#define WAKESTS_BROADCAST   0x02000000  // broadcast pkt wake event (ROSC) 
#define WAKESTS_ARPPKT      0x04000000  // ARP pkt wake event (ROSC) 
#define WAKESTS_PATRN0      0x08000000  // pattern0 match wake event (ROSC) 
#define WAKESTS_PATRN1      0x10000000  // pattern1 match wake event (ROSC) 
#define WAKESTS_PATRN2      0x20000000  // pattern2 match wake event (ROSC) 
#define WAKESTS_PATRN3      0x40000000  // pattern3 match wake event (ROSC) 
#define WAKESTS_MAGICPKT    0x80000000  // magic pkt wake event (ROSC) 

#define WAKEON_MASK         0x0000EFFF  // Alll wake-on bits

//**************************************************************
// PCR - Pause Control / Status Register.
//***************************************************************
#define PAUSEVAL_MASK           0x0000FFFF  // pause cntr value mask 

#define PS_TX_DP83818           0x00020000  // Manual pause frame load enable 
#define PS_TX                   0x00010000  // Manual pause frame load enable 

#define PS_DA                   0x20000000  // en pause  rcv sent to MAC addr
                                            //  or any pattern match (R/W) 
#define PS_MCAST                0x40000000  // en pause pkt rcv sent to IEEE
                                            //  reserved mcast address (R/W) 
#define RXPAUSE_EN              0x80000000  // en. pause frame reception (R/W) 

// pause threshold low values - rx data fifo  - DP83818+
#define PTHRESHLO_DFIFO_MASK    0x000C0000  // data fifo thresh low mask (R/W) 
#define PTHRESHLO_DFIFO_DIS     0x00000000  // low thresh disabled (R/W) 
#define PTHRESHLO_DFIFO512      0x00040000  // low thresh < 512 bytes (R/W) 
#define PTHRESHLO_DFIFO1024     0x00080000  // low thresh < 1K bytes (R/W) 
#define PTHRESHLO_DFIFO1536     0x000C0000  // low thresh < 1536 bytes (R/W) 

// pause threshold hi values - rx data fifo  - DP83818+
#define PTHRESHHI_DFIFO_MASK    0x00300000  // data fifo thresh hi mask (R/W) 
#define PTHRESHHI_DFIFO_DIS     0x00000000  // hi thresh disabled (R/W) 
#define PTHRESHHI_DFIFO512      0x00100000  // hi thresh >= 512 bytes (R/W) 
#define PTHRESHHI_DFIFO1024     0x00200000  // hi thresh >= 1K bytes (R/W) 
#define PTHRESHHI_DFIFO1536     0x00300000  // hi thresh >= 2K bytes (R/W) 

// pause threshold low values - rx status fifo  - DP83818+
#define PTHRESHLO_SFIFO_MASK    0x00C00000  // stat fifo thresh low mask (R/W) 
#define PTHRESHLO_SFIFO_DIS     0x00000000  // low thresh disabled (R/W) 
#define PTHRESHLO_SFIFO2PKTS    0x00400000  // low thresh < 2 pkts (R/W) 
#define PTHRESHLO_SFIFO4PKTS    0x00800000  // low thresh < 4 pkts (R/W) 
#define PTHRESHLO_SFIFO8PKTS    0x00C00000  // low thresh < 8 pkts (R/W) 

// pause threshold hi values - rx status fifo  - DP83818+
#define PTHRESHHI_SFIFO_MASK    0x03000000  // stat fifo thresh hi mask (R/W) 
#define PTHRESHHI_SFIFO_DIS     0x00000000  // hi thresh disabled (R/W) 
#define PTHRESHHI_SFIFO2PKTS    0x01000000  // hi thresh = 2 or more pkts (R/W) 
#define PTHRESHHI_SFIFO4PKTS    0x02000000  // hi thresh = 4 or more pkts (R/W) 
#define PTHRESHHI_SFIFO8PKTS    0x03000000  // hi thresh = 4 or more pkts (R/W) 



//**************************************************************
// RFCR - Receive Filter Control Register.
//***************************************************************
#define RXFLTRAM_ADDRMASK   0x000007ff

// FM - Need to check
#define MAX_FILTER_ROWS     32
#define MAX_FILTER_COLS     16
#define HASH_TABLE_INDEX    0x200       // beginning of the mcast/ucast hash
#define RCVPATTERNS_ADDR    0x280       // beginning of the receive pattern
                                        //  buffers 

#define ACCEPT_PTRNMATCH4   0x00008000  // en pattern match 0 (R/W) 
#define ACCEPT_PTRNMATCH5   0x00010000  // en pattern match 1 (R/W) 
#define ACCEPT_PTRNMATCH6   0x00020000  // en pattern match 2 (R/W) 
#define ACCEPT_PTRNMATCH7   0x00040000  // en pattern match 3 (R/W) 
#define IGNORE_ADDR_ULBIT   0x00080000  // ignore U/L bit in dest addr (R/W) 
#define UNICASTHASH_EN      0x00100000  // en unicast hash table (R/W) 
#define MCASTHASH_EN        0x00200000  // en multicast hash table (R/W) 
#define ACCEPT_ALLARP       0x00400000  // en reception of all ARP pkts (R/W) 

#define PATTRNMATCH_MASK    0x07800000  // pattern match en mask (R/W) 
#define ACCEPT_PTRNMATCH0   0x00800000  // en pattern match 0 (R/W) 
#define ACCEPT_PTRNMATCH1   0x01000000  // en pattern match 1 (R/W) 
#define ACCEPT_PTRNMATCH2   0x02000000  // en pattern match 2 (R/W) 
#define ACCEPT_PTRNMATCH3   0x04000000  // en pattern match 3 (R/W) 
#define ACCEPT_PERFECTMATCH 0x08000000  // en perfect match (R/W) 
#define ACCEPT_ALLUNICAST   0x10000000  // en reception of all unicast (R/W) 
#define ACCEPT_ALLMCAST     0x20000000  // en reception of all multicast (R/W) 
#define ACCEPT_ALLBCAST     0x40000000  // en reception of all broadcast (R/W) 
#define RXFLTR_EN           0x80000000  // ena recevie filtering.  
                                        //  Must be cleared to
                                        //   set other filter bits. (R/W) 

//**************************************************************
// RFDR - Receive Filter Data Register.
//***************************************************************
#define RXFLTRDATA_MASK     0x0000FFFF  // Recieve filter data mask (R/W) 
#define RXFLTRMSKBITS_MASK  0x00030000  // recive filter byte mask bits (R/W) 
#define RXFLTRMSKBIT_SHIFT  16          // required shift to point to the 
                                        //  mask bits 


//**************************************************************
// MIBC - MIB Control Register
//***************************************************************
#define MIBCNTRS_WRN    0x00000001  // Warning Test Indicator  (RO) 
#define MIBCNTRS_FREEZE 0x00000002  // freeze mib counters (WR0) 
#define MIBCNTRS_CLR    0x00000004  // clear all mib counters (W/R0) 
#define MIBCNTRS_STRB   0x00000008  // Strobe MIB counter (R/W) - Test Only 


//**************************************************************
// PQCR    - Priority Queuing Control Register
//***************************************************************
#define TXPRIOQ_EN  0x00000001  // en tx priority queuing (R/W) 
#define ROTPRIO_EN  0x00000002  // en rotating priority (i.e. 01230) If clear,
                                //  fixed priority (3 highest, 0 lowest) (R/W) 
#define Q0_QUOTA_SHIFT 8  // shift for Q0 quota (when ROTPRIO_EN set)
#define Q1_QUOTA_SHIFT 14 // shift for Q1 quota (when ROTPRIO_EN set)
#define Q2_QUOTA_SHIFT 20 // shift for Q2 quota (when ROTPRIO_EN set)
#define Q3_QUOTA_SHIFT 26 // shift for Q3 quota (when ROTPRIO_EN set)

//**************************************************************
// VRCR    -  VLAN Rx Control Reg
//***************************************************************
#define VTDEN 0x00000001  // VLAN tag detection enable
#define VTREN 0x00000002  // VLAN tag removal enable
#define DVTF  0x00000004  // Discard VLAN tagged frame
#define DUTF  0x00000008  // Discard untagged frame

//**************************************************************
// VTCR    -  VLAN Tx Control Reg
//***************************************************************
#define VGTI   0x00000001  // VLAN Global tag insertion
#define VPPTI  0x00000002  // VLAN per pkt tag insertion
#define VPAD68 0x00000004  // Tag VLAN frames to 68 bytes

#define VTCI_MASK  0x0000FFFF // tag mask
#define VTCI_SHIFT 16        // shift for tag contol field

//**************************************************************
// PHY Registers
//***************************************************************

// MII Base register offsets
#define MII_BMCR        0x00
#define MII_BMSR        0x01
#define MII_PHYIDR1     0x02
#define MII_PHYIDR2     0x03
#define MII_ANAR        0x04
#define MII_ANLPAR      0x05
#define MII_ANER        0x06
#define MII_ANNPTR      0x07

// BMCR - Basic Mode Control Register Definitions
#define PHY_RESET       0x8000     // Initiate soft reset of PHY
#define PHY_LOOPBACK    0x4000     // Put PHY in loopback mode
#define FORCE_SPEED_100 0x2000     // Force mode - 100Mbps
#define FORCE_SPEED_10  0x0000     // Force mode - 10Mbps
#define AUTONEG_ENABLE  0x1000     // Enable Auto-Neg
#define PHY_POWERDOWN   0x0800     // Power down the PHY
#define ISOLATE_PORT    0x0400     // Isolate this port from the MII
#define AUTONEG_RESTART 0x0200     // Restart Auto-Neg
#define FORCE_MODE_FD   0x0100     // Force mode - Full duplex
#define FORCE_MODE_HD   0x0000     // Force mode - Half duplex
#define COLL_TEST       0x0080     // Start Collision test

// BMSR - Basic Mode Status Register Definitions
#define AUTONEG_COMP    0x0020     // Auto nego process done
#define LINK_STATUS     0x0004     // Link Up
#define JABBER_DET      0x0002     // Jabber detected

// ANAR Definitions.
#define NP              0x8000     // Next Page Indication
#define ADV_RF          0x2000     // Advertise remote fault detection
#define ADV_ASM_DIR     0x0800     // Advertise Asymmetrical Pause
#define ADV_PAUSE       0x0400     // Advertise Symmetrical Pause
#define ADV_100BASET4   0x0200     // 100BASE-T4 Support
#define ADV_100BASET_FD 0x0100     // 100BASE-TX Full Duplex Support
#define ADV_100BASET_HD 0x0080     // 100BASE-TX Half Duplex Support
#define ADV_10BASET_FD  0x0040     // 10BASE-TX Full Duplex Support
#define ADV_10BASET_HD  0x0020     // 10BASE-TX Half Duplex Support
#define PSB             0x0001     // Protocol Selection - 802.3u

// PHYSTS Definitions - Some uncommon bits are not populated
#define POL_STS         0x1000     // Set when Inverted polarity is detected
#define INT_STS         0x0080     // Set when an internal interrupt is pending
#define RF_STS          0x0040     // Set when remote fault condition is 
                                   //  detected
#define JABBER_STS       0x0020    // Set when Jabber detected on line
#define AUTONEG_DONE_STS 0x0010    // Set when Auto-Neg is complete
#define LOOPBACK_STS     0x0008    // Set when PHY is in loopback mode
#define DUPLEX_FULL_STS  0x0004    // Set for Full duplex, reset for half
#define SPEED_10_STS     0x0002    // Set for 10Mbps, reset for 100Mbps
#define LINK_STS         0x0001    // Set when valid link is established

// MICR Definitions
#define PHY_INT          0x0002    // Propagate PHY intr to MAC
#define TINT             0x0001    // Indicate PHY to generate test intr

// MISR Definitions
#define MSK_LINK         0x4000    // Mask Link interrupt
#define MSK_ANC          0x0800    // Mask Auto-Neg done interrupt

#endif // _MPLREGS_H